• KSCI Review
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• v.2 no.1
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• pp.130-139
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• 1995

This paper suggests the method to shorten the search area by using edge detection and subimage partition. For the purpose reduce encoding time, The Domain areas are reduced 1/64 by partitioning original image to subimage, and classified them into edge area and shade area so that detect only the area in the same class. for achieving an encoding with good fidelity, tried to differ the search method as the threshold value of edge which is included in subimage, and compared the compression rate and fidelity when set the size of range block as $4{\times}4$ and $8{\times}8$.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.06a
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• pp.260-261
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• 2018

MPEG과 VCEG은 차세대 비디오 부호화 표준 기술 개발를 위한 JVET(Joint Video Exploration Team)을 구성하여 현재 비디오 표준화인 HEVC 대비 높은 부호화 효율을 목표로 연구를 진행하며 CfP(Call for Proposal) 단계를 진행 중이다. JVET의 공통 플랫폼인 JEM(Joint Exploration Test Model)은 HEVC의 quad-tree 기반 블록 분할 구조를 대신하여 더 많은 유연성을 제공하는 QTBT(Quad-tree plus binary-tree)가 적용되었다. QTBT는 화면 내 부호화 효율을 높이기 위한 하나의 방법으로 휘도와 색차 신호에 대해 분할된 블록 구조를 지원한다. 이러한 방법은 채널 간 블록 분할 모양이 동일하거나 비슷한 경우에 중복되는 블록 분할 신호가 발생할 수 있는 단점이 있다. 따라서 본 논문에서는 화면 내 부호화에서 채널 간 유사도 비교를 이용하여 적응형 색차 블록 방법을 제안한다. 제안한 방법의 실험 결과로 JEM 6.0과 비교하여 CfE(Call for Evidence) 영상에서 평균 0.28%의 Y BD-rate 감소와 함께 평균 124.5%의 부호화 복잡도 증가를 확인하였다.

• Journal of Broadcast Engineering
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• v.20 no.2
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• pp.340-347
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• 2015

HEVC (High Efficiency Video Coding) achieves high coding efficiency by employing a quadtree-based coding unit (CU) block partitioning structure and various prediction units (PUs), and the determination of the best CU partition structure and the best PU mode based on rate-distortion (R-D) cost. However, the computation complexity of encoding also dramatically increases. In this paper, to reduce such encoding computational complexity, we propose three fast PU mode decision methods based on encoding information of upper depth as follows. In the first method, the search of PU mode of the current CU is early terminated based on the sub-CBF (Coded Block Flag) of upper depth. In the second method, the search of intra prediction modes of PU in the current CU is skipped based on the sub-Intra R-D cost of upper depth. In the last method, the search of intra prediction modes of PU in the lower depth's CUs is skipped based on the sub-CBF of the current depth's CU. Experimental results show that the three proposed methods reduce the computational complexity of HM 14.0 to 31.4%, 2.5%, and 23.4% with BD-rate increase of 1.2%, 0.11%, and 0.9%, respectively. The three methods can be applied in a combined way to be applied to both of inter prediction and intra prediction, which results in the complexity reduction of 34.2% with 1.9% BD-rate increase.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• 전자공학회논문지 IE
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• v.46 no.4
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• pp.57-65
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• 2009

This paper presents the image contrast enhancement technique suitable for local dimming backlight of small-sized mobile display while achieving the reduction of the power consumption. In addition to the large-sized TFT-LCD, small-sized one has adopted LED for backlight. Since, conventionally, LED was mounted on the side edge of a display panel, global dimming method has been widely used. However, recently, new advanced method of local dimming by placing the LED to the backside of the display panel and it raised the necessity of sub-blocked processing after partitioning the target image. When the sub-blocked image has low brightness, the supply current of a backlight LED is reduced, which gives both enhancement of contrast ratio and power consumption reduction. In this paper, we propose simple and improved image enhancement algorithm suitable for the small-sized mobile display. After partitioning the input image by equal sized blocks and analyzing the pixel information in each block, we realize the primary contrast enhancement by independently processing the sub-blocks using the information such as histogram, mean, and standard deviation values of luminance(Y) component. And then resulting information is transferred to each backlight control unit for local dimming to realize the secondary contrast enhancement as well as reduction of power consumption.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.708-714
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• 2000

In this paper, an one-dimensional VLSI array for high speed processing of fractal image compression algorithm based the quad-tree partitioning method is proposed. First of all, the single assignment code algorithm is derived from the sequential Fisher's algorithm, and then the data dependence graph(DG) is obtained. The two-dimension array is designed by projecting this DG along the optimal direction and the one-dimensional VLSI array is designed by transforming the obtained two-dimensional array. The number of Input/Output pins in the designed one-dimensional array can be reduced and the architecture of process elements(PEs) can he simplified by sharing the input pins of range and domain blocks and internal arithmetic units of PEs. Also, the utilization of PEs can be increased by reusing PEs for operations to the each block-size. For fractal image compression of 512X512gray-scale image, the proposed array can be processed fastly about 67 times more than sequential algorithm. The operations of the proposed one-dimensional VLSI array are verified by the computer simulation.

• Journal of Broadcast Engineering
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• v.19 no.5
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• pp.627-630
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• 2014

The latest video coding standard, high efficiency video coding (HEVC) achieves high coding efficiency by employing a quadtree-based coding unit (CU) block partitioning structure which allows recursive splitting into four equally sized blocks. At each depth level, each CU is partitioned into variable sized blocks of prediction units (PUs). However, the determination of the best CU partition for each coding tree unit (CTU) and the best PU mode for each CU causes a dramatic increase in computational complexity. To reduce such computational complexity, we propose a fast PU decision algorithm that early terminates PU search. The proposed method skips the computation of R-D cost for certain PU modes in the current CU based on the best mode and the rate-distortion (RD) cost of the upper depth CU. Experimental results show that the proposed method reduces the computational complexity of HM12.0 to 18.1% with only 0.2% increases in BD-rate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.7
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• pp.677-684
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• 2003

This paper addresses the subblock phase weighting(SPW) method to reduce the PAPR in OFDM system. This method divides the input block of OFDM signal into many subblocks and lower the peak power by weighting the phase of each subblocks properly. SPW method can be realized by only one IFFT. PAPR reduction performance is novelly examined when the adjacent, interleaved and random subblock partitioning schemes are used in the SPW system. The random subblock partition scheme has the most effective. More subblocks can effectively reduce the PAPR, but there is a problem that the processing time of iteration is increased. We propose a new weighting factor combination of the complementary sequence characteristic with threshold technique. OFDM data can be recovered by the inserted side information of weighting factor in the feed forward type. Also, BER performance of this SPW system is analyzed when error happens in the side information.

• KOREAN JOURNAL OF CROP SCIENCE
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• v.43 no.1
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• pp.38-43
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• 1998

This study examined root growth and distribution under the direct seeding of rice cultivars developed in Korea, Japan, and the U.S. Cultivars from the U.S., especially 'M202' and 'Caloro', had a high ratio of the dry matter partitioning for root and top plant components. Caloro had high root and top growth. 'Koshihikari' from Japan showed the lowest ratio of R/T (root/total dry matter) due to the small amount of root and top plant growth. Most Japanese cultivars except transplanted 'Hatsuboshi' showed low ratio of R/T. Patterns of root distribution for each soil block were recorded by the root box-pin board method. Roots of all cultivars were distributed in blocks A, C, and E in the middle of box, i.e., just below the plant base. Roots of 'Dongjin', M202, and Caloro were distributed deeper than the others. Roots of transplanted Hatsuboshi developed much better than direct seeded Hatsuboshi. Total root weight density was highest in Caloro followed by Dongjin, 'Gancheok', 'Calrose', and the others. The root density of Caloro was twice as much as those of the others except Dongjin. According to cumulative percentages of root distribution on each soil layer, roots of most cultivars were distributed below 20cm. The U.S. cultivars showed vertically well developed root systems as compared to others. A large amount of roots were distributed in the top 15cm of soil layer for Hatsuboshi and Koshinikari, and their root systems appeared to be shallow. In contrast, the rates of root distribution in the top 10cm of soil layer were low for Dongjin, Calrose, and Caloro. These cultivars had relatively deep root systems.

• Journal of Broadcast Engineering
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• v.12 no.3
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• pp.278-288
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• 2007

We propose the fast full search algorithm that reduces the computational load of the block matching algorithm which is used for a motion estimation in the video coding. Since the conventional spiral search method starts searching at the center of the search window and then moves search point to estimate the motion vector pixel by pixel, it is good for the slow motion picture. However we proposed the efficient motion estimation method which is good for the fast and slow motion picture. Firstly, when finding the initial threshold value, we use the expanded predictor that can approximately calculate minimum threshold value. The proposed algorithm estimates the motion in the new search order after partitioning the search window and adapt the directional search order in the re-divided search window. At the result, we can check that the proposed algorithm reduces the computational load 94% in average compared to the conventional spiral full search algorithm without any loss of image quality.