• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.2
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• pp.200-205
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• 2006

Abstract This paper presents a personal identification method based on BMME and LDA for images acquired at anterior and posterior occlusion expression of teeth. The method consists of teeth region extraction, BMME, and pattern recognition forthe images acquired at the anterior and posterior occlusion state of teeth. Two occlusions can provide consistent teeth appearance in images and BMME can reduce matching error in pattern recognition. Using teeth images can be beneficial in recognition because teeth, rigid objects, cannot be deformed at the moment of image acquisition. In the experiments, the algorithm was successful in teeth recognition for personal identification for 20 people, which encouraged our method to be able to contribute to multi-modal authentication systems.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.56-65
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• 1999

This paper presents an architecture and its instruction set for a graphic coprocessor(GCP) which can be used for a multimedia server. The proposed instruction set employs parallel architecture concepts, such as SIMD and Superscalar. GCP consists of a scheduler and four functional units. The scheduler solves an instruction bottleneck problem causing by sharing with four general processors(GPs). GCP can execute up to 4 instructions in parallel. It consists of about 56,000 gates and operates at 30 MHz clock frequency due to speed limitation of SOG technology. GCP meets the real-time DCT algorithm requirement of the CIF image format and can process up to 63 frames/sec for the DCT Algorithm and 21 frames/sec for the Full Block matching Algorithm of the CIF image format.

• Journal of Broadcast Engineering
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• v.19 no.2
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• pp.227-239
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• 2014

This paper proposes an enhance prediction for conventional near-lossless coder to effectively lower external memory bandwidth in image processing SoC. First, we utilize an already reconstructed green component as a base of predictor of the other color component because high correlation between RGB color components usually exists. Next, we can improve prediction performance by applying variable block size prediction. Lastly, we use minimum internal memory and improve a temporal prediction performance by using a template dictionary that is sampled in previous frame. Experimental results show that the proposed algorithm shows better performance than the previous works. Natural images have approximately 30% improvement in coding efficiency and CG images have 60% improvement on average.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1886-1898
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• 2015

In today’s era of advanced technological developments, the threats to the authenticity and integrity of digital images, in a nutshell, the threats to the Image Forensics Research communities have also increased proportionately. This happened as even for the ‘non-expert’ forgers, the availability of image processing tools has become a cakewalk. This image forgery poses a great problem for judicial authorities in any context of trade and commerce. Block matching based image cloning detection system is widely researched over the last 2-3 decades but this was discouraged by higher computational complexity and more time requirement at the algorithm level. Thus, for reducing time need, various dimension reduction techniques have been employed. Since a single technique cannot cope up with all the transformations like addition of noise, blurring, intensity variation, etc. we employ multiple techniques to a single image. In this paper, we have used Fuzzy logic approach for decision making and getting a global response of all the techniques, since their individual outputs depend on various parameters. Experimental results have given enthusiastic elicitations as regards various transformations to the digital image. Hence this paper proposes Fuzzy based cloning detection and classification system. Experimental results have shown that our detection system achieves classification accuracy of 94.12%. Detection accuracy (DAR) while in case of 81×81 sized copied portion the maximum accuracy achieved is 99.17% as regards subjection to transformations like Blurring, Intensity Variation and Gaussian Noise Addition.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1187-1192
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• 2008

This paper proposes a fast motion estimation using an adaptive search region and a new three step search. The proposed method improved in the quality of motion compensation image as $0.43dB{\sim}2.19dB$, according as it predict motion of current block from motion vector of neigher blocks, and adaptively set up search region using predicted motion information. We show that the proposed method applied a new three step search pattern is able to fast motion estimation, according as it reduce computational complexity per blocks as $1.3%{\sim}1.9%$ than conventional method.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.8
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• pp.4005-4025
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• 2019

Copy-move forgery (CMF) in digital images is a detrimental tampering of artefacts that requires precise detection and analysis. CMF is performed by copying and pasting a part of an image into other portions of it. Despite several efforts to detect CMF, accurate identification of noise, blur and rotated region-mediated forged image areas is still difficult. A novel algorithm is developed on the basis of quaternion polar complex exponential transform (QPCET) to detect CMF and is conducted involving a few steps. Firstly, the suspicious image is divided into overlapping blocks. Secondly, invariant features for each block are extracted using QPCET. Thirdly, the duplicated image blocks are determined using k-dimensional tree (kd-tree) block matching. Lastly, a new technique is introduced to reduce the flat region-mediated false matches. Experiments are performed on numerous images selected from the CoMoFoD database. MATLAB 2017b is used to employ the proposed method. Metrics such as correct and false detection ratios are utilised to evaluate the performance of the proposed CMF detection method. Experimental results demonstrate the precise and efficient CMF detection capacity of the proposed approach even under image distortion including rotation, scaling, additive noise, blurring, brightness, colour reduction and JPEG compression. Furthermore, our method can solve the false match problem and outperform existing ones in terms of precision and false positive rate. The proposed approach may serve as a basis for accurate digital image forensic investigations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.364-370
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• 2002

In this paper, we propose a VLSI array architecture for high speed processing of FBMA. First of all, the sequential FBMA is transformed into a single assignment code by using the index space expansion, and then the dependance graph is obtained from it. The two dimensional VLSI array is derived by projecting the dependance graph along the optimal direction. Since the candidate blocks in the search range are overlapped with columns as well as rows, the processing elements of the VLSI array are designed to reuse the overlapped data. As the results, the number of data inputs is reduced so that the processing performance is improved. The proposed VLSI array has (N$^2$+1)${\times}$(2p+1) processing elements and (N+2p) input ports where N is the block size and p is the maximum search range. The computation time of the rat reference block is (N$^2$+2(p+1)N+6p), and the block pipeline period is (3N+4p-1).

• Journal of Broadcast Engineering
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• v.5 no.2
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• pp.247-259
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• 2000

This paper introduces a new technique that reduces the search times and Improves the accuracy of motion estimation using high temporal and spatial correlation of motion vector. Instead of using the fixed first search Point of previously proposed search algorithms, the proposed method finds more accurate first search point as to compensating searching area using high temporal and spatial correlation of motion vector. Therefore, the main idea of proposed method is to find first search point to improve the performance of motion estimation and reduce the search times. The proposed method utilizes the direction of the same coordinate block of the previous frame compared with a block of the current frame to use temporal correlation and the direction of the adjacent blocks of the current frame to use spatial correlation. Based on these directions, we compute the first search point. We search the motion vector in the middle of computed first search point with two fixed search patterns. Using that idea, an efficient adaptive predicted direction search algorithm (APDSA) for block matching motion estimation is proposed. In the experimental results show that the PSNR values are improved up to the 3.6dB as depend on the Image sequences and advanced about 1.7dB on an average. The results of the comparison show that the performance of the proposed APDSA algorithm is better than those of other fast search algorithms whether the image sequence contains fast or slow motion, and is similar to the performance of the FS (Full Search) algorithm. Simulation results also show that the performance of the APDSA scheme gives better subjective picture quality than the other fast search algorithms and is closer to that of the FS algorithm.

• Journal of Broadcast Engineering
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• v.3 no.1
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• pp.85-92
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• 1998

The block matching algorithm is the most popular motion estimation method in image sequence coding. In this paper, we propose a VLSI architecture. for implementing a recently proposed fast bolck matching algorith, which uses spatial correlation of motion vectors and hierarchical searching scheme. The proposed architecture consists of a basic searching unit based on a systolic array and two shift register arrays. And it covers a search range of -32~ +31. By using the basic searching unit repeatedly, it reduces the number of gatyes for implementation. For basic searching unit implementation, a proper systolic array can be selected among various conventional ones by trading-off between speed and hardware cost. In this paper, a structure is selected as the basic searching unit so that the hardware cost can be minimized. The proposed overall architecture is fast enough for low bit-rate applications (frame size of $352{\times}288$, 3Oframes/sec) and can be implemented by less than 20,000 gates. Moreover, by simply modifying the basic searching unit, the architecture can be used for the higher bit-rate application of the frame size of $720{\times}480$ and 30 frames/sec.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.4
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• pp.418-428
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• 2002

In this paper, we propose a motion-adaptive de-interlacing method using motion compensated interpolation. In a conventional motion compensated method, a simple pre-filter such as line averaging is applied to interpolate missing lines before the motion estimation. However, this method causes interpolation error because of inaccurate motion estimation and compensation. In the proposed method, EBMF(Edge Based Median Filter) as a pre-filter is applied, and new matching method, which uses two same-parity fields and opposite-parity field as references, is proposed. For further improvement, motion correction filter is proposed to reduce the interpolation error caused by incorrect motion. Simulation results show that the proposed method provides better performance than existing methods.