• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.190-193
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• 1988

Lucifer - type algorithms with variable length of block size are presented. They are investigated and compared in the viewpoint of the intersymbol dependence. The results show that the S-box and the number of rounds are very important factors in achieving the complete dependence.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.769-772
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• 2006

본 논문에서는 기존의 관용알고리즘을 비교 분석하고, 유무선 복합 통신망에서의 고속화를 위해 요구되는 암호알고리즘을 비교 분석한다. 기존에 사용되고 있는 블록 알고리즘의 경우, 고비도에 의해서 소프트웨어적 혹은 하드웨어적으로 설계하였을 경우, 현재의 이동통신망에 사용을 하였을 경우, 속도의 차이에 의해 사용이 불가능하다. 따라서, 본 논문에서는 이동통신 환경망에 적합한 블록알고리즘을 제안하고 분석하고자 한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.939-942
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• 2002

중간 노드들에서 통신 데이터를 불법으로 획득하는 스니핑에 대한 대안으로 암호화 통신에 대한 요구가 증가하고 있다. 이를 위해 본 논문에서는 암호화 통신을 위해 블록 암호 알고리즘을 사용한 패킷 암/복호화 모듈을 제시하고, SEED 알고리즘을 이용하여 리눅스에 구현한 사례를 기술한다. 이 모듈은 기존의 네트워크와 응용 프로그램에 영향을 주지 않고 암호화 통신 기능을 제공하기 위해 IP 패킷의 헤더 정보를 변경하는 방법을 사용한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.234-235
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• 2016

With the development of the Internet, the popularization of internet has become the new trend and enormously changed the way of human communication. There is a strong need for security. The following research will provide the definition and purpose of IoT and examine its security concerns, In this paper, we surveyed at energy consumption of lightweight block ciphers implemented in reconfigurable devices, and we analyze d the effects that round unrolling might have on the energy consumed during the encryption.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.1
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• pp.11-18
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• 2013

In order to prevent tampering and reverse engineering of executive code, this paper propose a new tamper resistant software mechanism. This paper presents a cryptographic MAC function and a relationship which has its security level derived by the importance of code block instead of by merely getting the encryption and decryption key from the previous block. In this paper, we propose a cryptographic MAC function which generates a dynamic MAC function key instead of the hash function as written in many other papers. In addition, we also propose a relationships having high, medium and low security levels. If any block is determined to have a high security level then that block will be encrypted by the key generated by the related medium security level block. The low security block will be untouched due to efficiency considerations. The MAC function having this dynamic key and block relationship will make analyzing executive code more difficult.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.307-311
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• 2004

This paper presents an efficient architecture that optimizes the design of SEED S-box using composite field arithmetic. SEED is the Korean standard 128-bit block cipher algorithm developed by Korea Information Security Agency. The nonlinear function S-box is the most costly operation in terms. of size and power consumption, taking up more than 30% of the entire SEED circuit. Therefore the S-box design can become a crucial factor when implemented in systems where resources are limited such as smart cards. In this paper, we transform elements in $GF(2^8)$ to composite field $GF(((2^2)^2)^2)$ where more efficient computations can be implemented and transform the computed result back to $GF(2^8)$. This technique reduces the S-box portion to 15% and the entire SEED algorithm can be implemented at 8,700 gates using Samsung smart card CMOS technology.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.313-316
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• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.11
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• pp.5717-5730
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• 2019

LBlock-s is the core block cipher of authentication encryption algorithm LAC, which uses the same structure of LBlock and an improved key schedule algorithm with better diffusion property. Using the differential properties of the key schedule algorithm and the cryptanalytic technique which combines impossible boomerang attacks with related-key attacks, a 15-round related-key impossible boomerang distinguisher is constructed for the first time. Based on the distinguisher, an attack on 22-round LBlock-s is proposed by adding 4 rounds on the top and 3 rounds at the bottom. The time complexity is about only 2^68.76 22-round encryptions and the data complexity is about 2⁵⁸ chosen plaintexts. Compared with published cryptanalysis results on LBlock-s, there has been a sharp decrease in time complexity and an ideal data complexity.

• ETRI Journal
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• v.29 no.6
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• pp.820-822
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• 2007

ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively. This letter presents an area-efficient unified hardware architecture of ARIA and AES. Both algorithms have 128-bit substitution permutation network (SPN) structures, and their substitution and permutation layers could be efficiently merged. Therefore, we propose a 128-bit processor architecture with resource sharing, which is capable of processing ARIA and AES. This is the first architecture which supports both algorithms. Furthermore, it requires only 19,056 logic gates and encrypts data at 720 Mbps and 1,047 Mbps for ARIA and AES, respectively.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.107-115
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• 2012

This paper proposes on the structure for reducing the circuit area and increasing the computation speed in implementing to hardware using the SEED algorithm of a 128-bit block cipher. SEED cipher can be implemented with S/W or H/W method. It should be important that we have minimize the area and computation time in H/W implementation. To increase the computation speed, we used the structure of the pipelined systolic array, and this structure is a simple thing without including any buffer at the input and output circuit. This circuit can record the encryption rate of 320 Mbps at 10 MHz clock. We have designed the circuit with the Verilog HDL coding showing the circuit performances in the figures and the table.