• Korean Journal of Digital Imaging in Medicine
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• v.16 no.1
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• pp.27-33
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• 2014

The purpose of this study evaluated the hemo-dynamic information within 30 seconds clinically in 3D breast MRI. From January to March 2014, A total of 40 people were examined at 1.5 Tesla(Philips, Medical System, Achieva, The Netherlands) MRI equipments using 16 channel SENSE breast coil. The imaging parameters on vibrant are fellow as: $TR/TE/FA^{\circ}$/Matrix size/Slice thickness/Slab($5ms/2ms/10^{\circ}/180{\times}139{\times}2mm/80$). This study used a Gadovist and injected it with injection speed of 4 ml /sec by auto injector with 15 ml saline flushing. Firstly, for the delay time study, it divided three different delay time from immediately, 20 seconds, and 30 seconds. In quantitative analysis, the ROI signal intensities of tumor and surrounding tissues were measured retrospectively. In qualitative analysis, the image quality was scored from 1 to 5 point by one experienced radiological technologists as a visual test. The significance level of each delay time was evaluated with a one-way ANOVA(p<0.05). In the visual test, score levels on 30 seconds delay time was a little bit higher than others(p<0.05). The signal intensity of the tumor were $1445{\pm}360$, $1410{\pm}320$, $1510{\pm}415$ on immediately, 20 seconds, and 30 seconds and score levels were $4.18{\pm}0.85$, $3.54{\pm}0.94$, $4.45{\pm}0.74$(p<0.05). The data on immediate images showed better results than that others(p<0.05). Conclusively, Although it has been high scored in 30sec delay time for visual test in order to avoid failure in 20second, 30seconds delay time after contrast media administration, we recommend that the DCE 3D breast MRI commence immediately.

• Journal of Broadcast Engineering
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• v.12 no.6
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• pp.574-584
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• 2007

As the real time multimedia service become more popular, the needs of transmission with low delay and high quality are getting more stronger. Among those video compression technologies, the rate control method dose an important role in getting the effective data transmitting and the high image quality. In this paper, we combined the feature of CBR and VBR coding methods to propose a new bit-rate control method witch allows each frame to generates bits in the defined fluctuation range and applies a scene change detection at a part of frame and also can maintain low-delay and high quality even if the perfect VBR transmission environment is not guaranteed. The experiment result shows the proposed algorithm provides more effective method than TMN8 in real time application.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.67-73
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• 2015

This paper presents a fully integrated 3 - 5 GHz IR-UWB(impulse radio ultra-wide band) RFIC for Location based system. The receiver architecture adopts the energy detection method and for high speed sampling, the equivalent time sampling technique using the integrated DLL(delay locked loop) and 4 bit ADC. The digitally synthesized UWB impulse generator with low power consumption is also designed. The designed IR-UWB RFIC is implemented on $0.18{\mu}m$ CMOS technology. The receiver's sensitivity is -85.7 dBm and the current consumption of receiver and transmitter is 32 mA and 25.5 mA respectively at 1.8 V supply.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• ETRI Journal
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• v.33 no.4
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• pp.528-536
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• 2011

In this paper, we analyze the location accuracy of real-time locating systems (RTLSs) in multipath environments in which the RTLSs comply with the ISO/IEC 24730-2 international standard. To analyze the location error of RTLS in multipath environments, we consider a direct path and indirect path, in which time and phase are delayed, and also white Gaussian noise is added. The location error depends strongly on both the noise level and phase difference under a low signal-to-noise ratio (SNR) regime, but only on the noise level under a high SNR regime. The phase difference effect can be minimized by matching it to the time delay difference at a ratio of 180 degrees per 1 chip time delay (Tc). At a relatively high SNR of 10 dB, a location error of less than 3 m is expected at any phase and time delay value of an indirect signal. At a low SNR regime, the location error range increases to 8.1 m at a 0.5 Tc, and to 7.3 m at a 1.5 Tc. However, if the correlation energy is accumulated for an 8-bit period, the location error can be reduced to 3.9 m and 2.5 m, respectively.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.25-32
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• 2014

In this paper, we proposed a partial-way set associative cache memory with an effective memory access time and low energy consumption. In the proposed set-associative cache memory, it is allowed to access only a 2-ways among 4-way at a time. Choosing ways to be accessed is made dynamically via the least significant two bits of the tag. The chosen 2 ways are sequentially accessed by the way selection bits that indicate the most recently referred way. Therefore, each entry in the way has an additional bit, that is, the way selection bit. In addition, instead of the 4-way LRU or FIFO algorithm, we can utilize a simple 2-way replacement policy. Simulation results show that the energy*delay product can be reduced by about 78%, 14%, 39%, and 15% compared with a 4-way set associative cache, a sequential-way cache, a way-tracking cache, and a way cache respectively.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.697-700
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• 1988

This paper describes the design of a hardware system for ECG feature extraction based on pipeline processor consisting of three computers. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggred detector. Four diagnostic parameters-heart, axis, and ST axis, and ST segment are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. Therefore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory units is designed to decrease the delay time caused by data transfer between processors and designed by which the delay time can be taken 1% of one clock period.

• Journal of Biomedical Engineering Research
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• v.9 no.1
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• pp.79-86
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• 1988

This paper describes the design of a hardware systenl for ECG feature extraction based on pipeline processor consistinsf of three microcomputers. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters parameters-heart rate, morPhology, axis, and 57 segment-are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. Therefore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory units is designed to decrease the delay time caused by data transfer between processors and designed by which the delay time can be taken Loye of one clock period.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.1
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• pp.44-49
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• 2011

The need of data transmission in oceans and other underwater mediums are increasing day by day, so as the research. The underwater medium is very different from that of air. Propagation of electromagnetic wave in water or underground is very difficult because of the conductivity of the propagation materials. In this case, we usually use acoustic signals as ultrasonic but, they are not easy to transfer long distance with coherent method because of time varying multipaths, Doppler effects and attenuations. So, we use non-coherent methods such as FSK or ASK to communicate between long distances. But, as the propagation speed of acoustic wave is very slow, BW of the channel is narrow. It is very hard to guaranty the enough speed for the transmission of digital image data. In previous studies, we proposed this data communication protocol theoretically. In this paper, an underwater channel is modeled and this protocol is tested in this channel condition. The results show that the protocol is 4-6 times faster than ASK. Some relations and results are shown depending on the data length, channel length, bit rate etc.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.45-48
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• 2003

We can easily buy network system for high performance micro-processor, progress computer architecture is caused of high bandwidth and low delay time. Coupling PC-based commodity technology with distributed computing methodologies provides an important advance in the development of single-user dedicated systems. Lately Network is joined PC or workstation by computers of high performance and low cost. Than it make intensive that Cluster system is resembled supercomputer. Unix, Linux, BSD, NT(Windows series) can use Cluster system OS(operating system). I'm chosen linux gain low cost, high performance and open technical documentation. This paper is benchmark performance of Beowulf clustering by UltraSPARC-1K(64bit-RISC processor). Benchmark tools use MPI(Message Passing Interface) and NetPIPE. Beowulf is a class of experimental parallel workstations developed to evaluate and characterize the design space of this new operating point in price-performance.