• Journal of Digital Contents Society
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• v.16 no.5
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• pp.775-781
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• 2015

EBS started 2HD MMS experimental broadcasting for the first time in Korea on Feb. 11, 2015. It uses the picture compression technique based on MPEG-2 CODEC, and applies the result of the experiment about variable bit rates and changes according to the scanning types, 1080i and 720p. But when changing channels, the delay in displaying picture occurs because of the operation of the variable GOP on MMS broadcasting, which optimizes image quality by application variable bit rates. In this study, verified the relationship between the decoding time of I frames and the GOP set in the encoding step by experimenting and analyzing ON-AIR TS. By using the verification data and adjusts the Encoder GOP parameters, improved the different video display time delays according to the scanning mode 1080i and 720p.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.2
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• pp.49-61
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• 2009

Finite Field multiplication operation is one of the most important operations in the finite field arithmetic. Recently, Fan and Dai introduced a Shifted Polynomial Basis(SPB) and construct a non-pipeline bit-parallel multiplier for $F_{2^n}$. In this paper, we propose a new bit-parallel shifted polynomial basis type I and type II multipliers for $F_{2^n}$ defined by an irreducible trinomial $x^{n}+x^{k}+1$. The proposed type I multiplier has more efficient the space and time complexity than the previous ones. And, proposed type II multiplier have a smaller space complexity than all previously SPB multiplier(include our type I multiplier). However, the time complexity of proposed type II is increased by 1 XOR time-delay in the worst case.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.37-42
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• 2008

In this paper, we propose a partial product addition method using variable groups in the design of operators such as multipliers and digital filters. By this method, full adders can be replaced with simple logic circuits. To show the efficiency of the proposed method, we applied the method to the design of squarers and precomputer blocks of FIR filters. In case of 7 bit and 8 bit squarers, it is shown that by the proposed method, area, power and delay time can be reduced up to {22.1%, 20.1%, 14%} and {24.7%, 24.4%, 6.7%}, respectively, compared with the conventional method. The proposed FIR precomputer circuit leads to up to {63.6%, 34.4%, 9.8%} reduction in area, power consumption and propagation delay compared with previous method.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.291-298
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• 2023

SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.

• Korean Journal of Optics and Photonics
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• v.16 no.3
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• pp.287-294
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• 2005

In this paper, an optical true time-delay (TTD) for two-dimensional (2-D) phased array antennas (PAAs), composed of a multi-wavelength optical source and a fiber optic delay line matrix consisting of $2\times2$ optical switches with optical fiber connected between cross ports, has been proposed. A 2-bit $\times4-bit$ optical TTD for 10-GHz 2-D PAAs has been implemented by cascading a wavelength dependent TTD (WD-TTD) and a wavelength independent TTD (WI-TTD). The unit time delay for WD-TTD and WI-TTD have been chosen as ${\Delta}T=12ps$ and $\Delta\tau=6ps$, respectively. Time delay have been measured at all radiation angles. The maximum delay error for WD-TTD was measured to be 3 ps due to jitter incurred from gain switching. For the case of WI-TTD, error was within ${\pm}\;1\;ps$. The proposed optical TTD for a 2-D PAA has the following advantages: 1) higher gain compared to one-dimensional linear PAAs, 2) stabilization of optical power and wavelength by using a multi-wavelength optical source, and 3) fast beam scan and simple operation due to electronic control of the $2\times2$ optical switches matrix on a column-by-column basis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.726-742
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• 2000

A novel rte control algorithm consisting of two major components, i.e. a variable encoding frame rate method and a hybrid DCT/wavelet I-frame coding scheme, is proposed in this work for low bit rate video coding. Most existing rate control algorithms for low bit rate video focus on bit allocation at the macroblock level under a constant frame rate assumption. The proposed rate control algorithm is able to adjust the encoding frame rate at the expense of tolerable time-delay. Furthermore, an R-D optimized hybrid DCT/wavelet scheme is used for effective I-frame coding. The new rate-control algorithm attempts to achieve a good balance between spatial quality and temporal quality to enhance the overall human perceptual quality at low bit rates. It is demonstrated that the rate control algorithm achieves higher coding efficiency at low bit rates with a low additional computational cost. The variable frame rate method and hybrid I-frame coding scheme are compatible with the bi stream structure of H.263+.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.59-70
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• 1993

An efficient test method based on march test is presented to cover line leakage failures associated with bit and word lines or mega bit DRAM chips. A modified column march (Y-march) pattern is derived to improve fault coverage against the data retention failure. Time delay concept is introduced to develop a new column march test algorithm detecting various data retention failures. A built-in test circuit based on the column march pattern is designed and verified using logic simulation, confirming correct test operations.

• Journal of IKEEE
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• v.23 no.2
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• pp.681-686
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• 2019

This paper proposes a CMOS temperature sensor using inverter delay chains of the same size based on the pulse shrinking method. A temperature-pulse converter (TPC) uses two different temperature delay lines with inverter chains to generate a pulse in proportion to temperature, and a time-digital converter (TDC) shrinks the pulse using inverter chains of the same size to convert pulse width into a digital value to be insensitive to process changes. The chip was implemented with a $0.49{\mu}m{\times}0.23{\mu}m$ area using a $0.35{\mu}m$ CMOS process with a supply voltage of 3.3V. The measurement results show a resolution of $0.24^{\circ}C/bit$ for 9-bit data for a temperature sensor range of $0^{\circ}C$ to $100^{\circ}C$.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.131-135
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• 2000

본 논문에서는 고성능 고정 소수점 DSP (Digital Signal Processor) 코어인 Vincent6 코어 [1]를 이용하여 ITU-T C.728 음성 부호화기를 실시간으로 구현하였다 G.728 은 16 kb/s전송률의 ITU-T표준 음성 부호화기이며, 입력신호는 8 kHz로 샘플링되며 샘플 당 16 bit 로 양자화된 PCM 신호이다. G.728 은 LD-CELP(Low Delay Code Excited Linear Prediction)라고도 하며, 알고리 듬 delay는 0.625ms 이다. Vincent6 DSP core 는 VLIW (Very-Long Instruction Word) 특성을 가지므로 다중 명령 (multiple instruction)을 수행할 수 있다 이를 위해서 G.728 annex G를 이용하여 고정 소숫점 연산으로 코드를 작성한 후, 이를 vincent6 어셈블리 코드로 구현하였다. 최종적으로 구현된 코드는 ITU-T 의 test vector 에 대 해 bit exact 한 결과를 보이며 34 MCPS (Million Cycles Per Second)의 계산량을 가지며 사용 메모리크기는 데이터 메모리가 약 9KByte, 프로그램 메모리가 약 57 KByte 이다.

• Proceedings of the Optical Society of Korea Conference
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• 2003.02a
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• pp.320-321
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• 2003

위성통신 및 무선통신에서 안테나의 수신 감도를 향상시키기 위한 노력은 계속되어 왔다. 안테나의 지향성을 높이기 위하여 다수의 동형 단위 안테나들을 일정 방향으로 배열하여 안테나를 기계적으로 회전시키지 않고, 고정된 다수의 동형 단위 안테나들에서 방사되는 전파의 위상을 전자적으로 변화시켜 방사 빔을 주사하는 방법, 즉 위상배열 안테나(Phased Array Antenna)를 널리 사용하고 있다. 위상배열 안테나의 단위 안테나에서 방사되는 전파의 위상을 변화시키기 위해선 실시간 시간지연 시스템이 필요하다. (중략)