• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.668-672
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• 2009

In wireless ad-hoc network, knowing the available bandwidth of the time varying channel is imperative for live video streaming applications. This is because the available bandwidth is varying all the time and strictly limited against the large data size of video streaming. Additionally, adapting the encoding rate to the suitable bit-rate for the network, where an overlarge encoding rate induces congestion loss and playback delay, decreases the loss and delay. While some effective rate controlling methods have been proposed and simulated well like VTP (Video Transport Protocol) [1], implementing to cooperate with the encoder and tuning the parameters are still challenging works. In this paper, we show our result of the implementation experiment of VTP based encoding rate controlling method and then introduce some techniques of our parameter tuning for a video streaming application over wireless environment.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.526-529
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• 1998

This paper describes new sense amplifier with fast sensing delay time of 0.54ns and 32kb CMOS embedded SRAM with 4.67ns access time for a 3-V powr supply. It was achieved using the sense amplifier with multiple point sensing scheme and high speed bit-line scheme. The sense amplifier saves 25% of the power dissipation compared with the conventional one while maintaining a very short sensing delay. The SRAM uses 0.5.mu.m double-polysilicon and triplemetal CMOS process technology. A die size is 1.78mm*2.13mm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.49-54
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• 2008

In cryptosystems based on finite fields, a modular multiplication operation is the most crucial part of finite field arithmetic. Also, in multipliers with resource constrained environments, bit-serial output structures are used in general. This paper proposes two efficient bit-serial output multipliers with the polynomial basis representation for irreducible trinomials. The proposed multipliers have lower time complexity compared to previous bit-serial output multipliers. One of two proposed multipliers requires the time delay of $(m+1){\cdot}MUL+(m+1){\cdot}ADD$ which is more efficient than so-called Interleaved Multiplier with the time delay of $m{\cdot}MUL+2m{\cdot}ADD$. Therefore, in elliptic curve cryptosystems and pairing based cryptosystems with small characteristics, the proposed multipliers can result in faster overall computation. For example, if the characteristic of the finite fields used in cryprosystems is small then the proposed multipliers are approximately two times faster than previous ones.

• Journal of Satellite, Information and Communications
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• v.1 no.1
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• pp.20-25
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• 2006

The link of Geostationary Communication Satellite has transit delay and noise environments by physical distance. This situation exerts an influence on the degradation of baseband performance of Earth Station. Therefore, it is very important that degradation of baseband performance is grasped previously. This paper is presented that developed the simulator which can evaluate the baseband performance of earth station of a military satellite communication system during the current development. The simulator can mock delay on a satellite channel and bit errors without being used actual satellite links.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.7
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• pp.365-371
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• 2014

Chaos communication system is possible to improve the system security by using chaos signal. Further, it is possible to reduce the possibility of eavesdropping, and have strong characteristics from interference signal and jamming signal. However, BER(Bit Error Rate) performance of chaos system is worse than digital communication system. By this reason, researches in order to improve the BER performance of chaos communication system are being actively studied. In previous studies, we proposed a novel chaos map for BER performance improvement, and called it 'Boss map'. Also, we proposed a novel chaos transceiver for BER performance improvement. However, BER performance is evaluated differently according to delay time in transceiver. Therefore, in order to use Boss map effectively, we should find the optimal delay time in proposed chaos transceiver. In this paper, when Boss map is used, we evaluate BER performance of CDSK(Correlation Delay Shift Keying) system and novel chaos transceiver according to delay time. After evaluation of BER performance according to delay time, we find a delay time that is possible to have best BER performance in CDSK system and novel chaos transceiver.

• ETRI Journal
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• v.19 no.4
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• pp.344-362
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• 1997

The delay which is one of the quality of service parameters is considered to be a crucial factor for the effective usage of real-time audio and video streams in interactive multimedia collaborations. Among the various causes of the delay, we focus in this paper on the local delay concerned with the schemes which handle continuous inflow of encoded data from constant or variable bit-rate audio and video encoders. We introduce two kinds of implementation approaches, pull model and push model. While the pull model periodically pumps out the incoming data from the system buffer, the push model receives events from the device drivers. From our experiments based on Windows NT 3.51, it is shown that the push model outperforms the other for both constant and variable bit-rate streams in terms of the local delay, when the system suffers reasonable loads. We interpret this experimental data with M/G/1 multiple vacation queuing theories, and show that it is consistent with the queuing theoretic interpretations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.205-210
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• 2001

In this paper, a novel compound mode logic based on the advantage of both CMOS logic and pass-transistor logic(PTL) is proposed. From the experimental results, the power-delay products of the compound mode logic is about 22% lower than that of the conventional CMOS logic, when we design a full adder. With the proposed logic, a high performance 32$\times$32-bit multiplier has been fabricated with 0.6um CMOS technology. It is composed of an improved sign select Booth encoder, an efficient data compressor based on the compound mode logic, and a 64-bit conditional sum adder with separated carry generation block. The Proposed 32$\times$32-bit multiplier is composed of 28,732 transistors with an active area of 1.59$\times$1.68 mm2 except for the testing circuits. From the measured results, the multiplication time of the 32$\times$32-bit multiplier is 9.8㎱ at a 3.3V power supply, and it consumes about 186㎽ at 100MHz.

• Journal of the Korea Computer Industry Society
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• v.7 no.5
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• pp.513-520
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• 2006

In this paper, we propose a novel real-time frame-layer rate control algorithm using sliding window method for low bit rate video coding. The proposed rate control method performs bit allocation at the frame level to minimize the average distortion over an entire sequence as well as variations in distortion between frames. A new frame-layer rate-distortion model is derived, and a non-iterative optimization method is used for low computational complexity. In order to reduce the quality fluctuation, we use a sliding window scheme which does not require the pre-analysis process. Therefore, the proposed algorithm does not produce time delay from encoding, and is suitable for real-time low-complexity video encoder. Experimental results indicate that the proposed control method provides better visual and PSNR performance than the existing TMN8 rate control method.

• Journal of the Korea Society of Computer and Information
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• v.24 no.8
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• pp.137-142
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• 2019

This paper proposed bitmap based spatial data transmission scheme in need of rapid transmission through network in mobile environment that use and creation of data are frequently happen. Former researches that used clustering algorithms, focused on providing service using spatial data can cause delay since it doesn't consider the transmission speed. This paper guaranteed rapid service for user by convert spatial data to bit, leads to more transmission of bit of MTU, the maximum transmission unit. In the experiment, we compared arithmetically default data composed of 16 byte and spatial data converted to bitmap and for simulation, we created virtual data and compared its network transmission speed and conversion time. Virtual data created as standard normal distribution and skewed distribution to compare difference of reading time. The experiment showed that converted bitmap and network transmission are 2.5 and 8 times faster for each.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.454-464
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• 2002

In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.