• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.2
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• pp.213-217
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• 2015

Microwave Photonic(MWP) filters capable of use a bandpass filter or a notch filter with large bandwidth have been proposed. 4-lines${\times}$2-bit fiber-optic delay lines with a unit time-delay difference of 50 ps were experimentally realized. By changing the time-delay difference and the coefficients of microwave-modulated optical signals, the bandpass and notch filters were implemented and characterized.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1868-1879
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• 1996

There are limitations to process high bandwidth traffic in B-ISDN with mesh- topology single bus architecture of current mobile communication system. And, it is impossible to import ATM switch using fixed length packet rather than variable length packet. Some implementations are able to process variable length packet, but there are some problems such as pre-processing for synchronization and bit delay. In this paper, we design a concentrator that can manipulate variable length packet without additional pre-process. There is on bit delay for packet starting signal in input interface, So it is more efficient to process packets, such that the concentrator can reduce he processing time as $\ulcornerlog2N\lrcorne＋1$ bit-time rather than N bit-time delay in ordinary concentrator. It is expected that the mobile communication system with partial mesh topology bus adopting the knockout switch architecture can process high bandwidth traffic in B-ISDN.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.4
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• pp.34-42
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• 1981

A 512-bit Task Programmable ROM has been designed and fabricated using PMOS technology. The content of the memory was written through the gate pattern during the fabrication process, and was checked by displaying the output of the chip on an oscilloscope with 512(32$\times$16) matrix points. The operation of the chip was surcessful with operating voltage from -6V to -l2V, The power consumption and propagation delay time have been measured to be 3mW and 13 $\mu$sec, respectively at -6 Volt. The power consunption increased to 27mW and propagation delay time decreased to 3$\mu$sec at -12V. The output of the chip was capable of driving the input of a TTL gate directly and retained a high impedence state when the chip solect function disabled the output.

• Journal of information and communication convergence engineering
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• v.5 no.1
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• pp.54-58
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• 2007

A real-time frame-layer rate control algorithm with a token bucket traffic shaper is proposed for distortion variation minimization. The proposed rate control method uses a non-iterative optimization method for low computational complexity, and performs bit allocation at the frame level to minimize the average distortion over an entire sequence as well as variations in distortion between frames. The proposed algorithm does not produce time delay from encoding, and is suitable for real-time low-complexity video encoder. Experimental results indicate that the proposed control method provides better visual and PSNR performances than the existing rate control method.

• The Journal of the Acoustical Society of Korea
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• v.37 no.2
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• pp.110-117
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• 2018

In this paper, we propose a low delay window switching MDCT (Modified Discrete Cosine Transform) method for speech/audio coder. The window switching algorithm is used to reduce the degradation of sound quality in non-stationary trasient duration and to reduce the algorithm delay by using the low delay TDAC (Time Domain Aliasing Cancellation). While the conventional window switching algorithms uses overlap-add with different lengths, the proposed method uses the fixed overlap add length. It results the reduction of algorithm delay by half and 1 bit reduction in frame indication information by using 2 window types. We apply the proposed algorithm to G.729.1 based on MDCT in order to evaluate the performance. The propose method shows the reduction of algorithm delay by half while speech quality of the proposed method maintains same as the conventional method.

• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.28-37
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• 1999

In this paper. we developed a delay test architecture and test procedure for clocked 5-bit asynchronous counter circuit based on boundary scan architecture. To develope, we analyze the problems of conventional method on delay test for clocked sequential circuit in boundary scan architecture. This paper discusses several problems of delay test on boundary scan architecture for clocked sequential circuit. Conventional test method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a delay test architecture and test procedure, is based on a clock count-generation technique to generate continuous clocks for clocked input of CUT. The simulation results or 5-bit counter shows the accurate operation and effectiveness of the proposed delay test architecture and procedure.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.10
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• pp.1061-1070
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• 2009

In this paper, we have designed TDL(True-time Delay Line) for eliminating beam-squint occurring in active phased array antenna with large electrical size operated in wide bandwidth, and have tested its electrical performance. The proposed TDL device is composed of 4-bit microstrip delay line structure and MMIC amplifier for compensation of the delay-line loss. The measured results of gain and phase versus delay state satisfy the electrical requirements, also P1dB output power and noise figure meet the requirement. To verify the performance of fabricated TDL, we have simulated the beam patterns of wide-band active phased array antenna using the measured results and have certified the beam pattern compensation performance. As a result of simulated beam pattern compensation with respect to the 675.8 mm size antenna which is operated in X-band, 800 MHz bandwidth, we have reduced the beam squint error of ${\pm}1^{\circ}$ with ${\pm}0.1^{\circ}$. So this TDL module is able to be applied to active phase array antenna system.

• Journal of Korea Multimedia Society
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• v.21 no.3
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• pp.415-422
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• 2018

Advances of telecommunication technology bring various changes in journalism field. Reporters started to gather, edit, and transmit content to main server in media company using hand-held smart media and notebook computer. This paper tried to testify valid bit-rate of visual news content using LTE network and mobile phone. Field news like natural disasters need real-time transmission of video content. But broadcasting company normally use heavy ENG system and transmission satellite trucks. We prepared and experimented different types of visual content that has different bit-rates. Transmission tool was LU-60HD mobile system of LiveU Corporation. Transmission result shows that bit-rate of 2Mbps news content is not suitable for broadcasting and VBR (Variable Bit Rate) transmission has better definition quality than CBR (Constant Bit Rate) method. Three different bit-rate of VBR transmission result shows that 5Mbps clip has better quality than 1Mbps and 3Mbps. The higher bit-rate, the better video quality. But if the content has much movements, that cause delay and abnormal quality of video. So optimizing the balance between stability of signal and quality of bit-rate is crucial factor of real-time broadcasting news gathering business.

• Journal of Advanced Navigation Technology
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• v.9 no.2
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• pp.156-163
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• 2005

In this paper, we analyzed the performance of VDL mode 3 system model whose specification is defined by ICAO(International Civil Aviation Organization). For performance evaluation, we obtained BER(Bit Error Rate), transmission delay time, burst retransmission rate and throughput. From the analysis result, we could explicitly define relationships among BER, transmission delay time, throughput and burst restransmission rate. In addition, it became known that V/D retransmission rate and throughput are closely related in down link channel.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.733-736
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• 1999

In this Paper, Bit selectable and Bi-directional Interface Port is described, which can communicate data with the peripheral devices. Specially A description of the asynchronous design method is given to remove the clock skew phenomenon and the output asynchronous control method which finds the optimal clock and controls all the enable signal of the output pins at the same time is presented. Using this technique interface ports have delay time of less-than 0.5㎱.