• Title/Summary/Keyword: Bipolar process

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Fabrication Process of Rheology Material Thin Plate Using Vacuum Low Pressure Die-casting Process with Electromagnetic Stirring (레오로지 박판의 전자교반을 응용한 진공 저압주조 제조공정)

  • Jang, Sin-Kyu;Bae, Jung-Woon;Jin, Chul-Kyu;Kang, Chung-Gil
    • Journal of Korea Foundry Society
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    • v.32 no.1
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    • pp.16-23
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    • 2012
  • In this study, we develop the lower pressure die casting with rheo-forming process of A356 aluminum alloy and vacuum system which can control the crystal size and obtain the high strengthened-light material. Using this process, we fabricate the thin plate for bipolar plate through the low pressure die casting with electromagnetic stirring and vacuum-evacuation which can control the crystal grain by electromagnetic stirring. Thin plate ($110mm{\times}130mm{\times}1mm$) is fabricated by this process. The average Vickers hardness of thin plate is about 77 HV.

Degradation of the SiGe hetero-junction bipolar transistor in SiGe BiCMOS process (실리콘-게르마늄 바이시모스 공정에서의 실리콘-게르마늄 이종접합 바이폴라 트랜지스터 열화 현상)

  • Kim Sang-Hoon;Lee Seung-Yun;Park Chan-Woo;Kang Jin-Young
    • Journal of the Korean Vacuum Society
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    • v.14 no.1
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    • pp.29-34
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    • 2005
  • The degradation of the SiGe hetero-junction bipolar transistor(HBT) properties in SiGe BiCMOS process was investigated in this paper. The SiGe HBT prepaired by SiGe BiCMOS process, unlike the conventional one, showed the degraded DC characteristics such as the decreased Early voltage, the decreased collector-emitter breakdown voltage, and the highly increased base leakage current. Also, the cutoff frequency(f/sub T/) and the maximum oscillation frequency(f/sub max/) representing the AC characteristics are reduced to below 50%. These deteriorations are originated from the change of the locations of emitter-base and collector-base junctions, which is induced by the variation of the doping profile of boron in the SiGe base due to the high-temperature source-drain annealing. In the result, the junctions pushed out of SiGe region caused the parastic barrier formation and the current gain decrease on the SiGe HBT device.

A Study of the Electrical Characteristics of WOx Material for Non-Volatile Resistive Random Access Memory (비-휘발성 저항 변화 메모리 응용을 위한 WOx 물질의 전기적 특성 연구)

  • Jung, Kyun Ho;Kim, Kyong Min;Song, Seung Gon;Park, Yun Sun;Park, Kyoung Wan;Sok, Jung Hyun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.29 no.5
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    • pp.268-273
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    • 2016
  • In this study, we observed current-voltage characteristics of the MIM (metal-insulator-metal) structure. The $WO_x$ material was used between metal electrodes as the oxide insulator. The structure of the $Al/WO_x/TiN$ shows bipolar resistive switching and the operating direction of the resistive switching is clockwise, which means set at negative voltage and reset at positive voltage. The set process from HRS (high resistance state) to LRS (low resistance state) occurred at -2.6V. The reset process from LRS to HRS occurred at 2.78V. The on/off current ratio was about 10 and resistive switching was performed for 5 cycles in the endurance characteristics. With consecutive switching cycles, the stable $V_{set}$ and $V_{reset}$ were observed. The electrical transport mechanism of the device was based on the migration of oxygen ions and the current-voltage curve is following (Ohm's Law ${\rightarrow}$ Trap-Controlled Space Charge Limited Current ${\rightarrow}$ Ohm's Law) process in the positive voltage region.

A Design of Novel Class-A bipolar $CCII{\pm}$ and Its Application to output Current Controllable CCII+ (새로운 A급 바이폴라 $CCII{\pm}$와 이를 이용한 출력 전류 제어 가능한 CCII+ 설계)

  • Cha, Hyeong-Woo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.11
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    • pp.48-56
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    • 2011
  • Novel class-A bipolar current conveyor($CCII{\pm}$) with differential current output and its application to output current controllable CCII+ for electronic tuning systems are designed. The $CCII{\pm}$ is consists of conventional CCII+ and complementary cross current sources. The CCII+ with controllable the output current consists of the $CCII{\pm}$ and a current gain amplifier with single-ended current output. The simulation result shows that the $CCII{\pm}$ has current input impedance of $1.9{\Omega}$ and a good linearity for voltage and current follower. The proposed CCII+ has 3-dB cutoff frequency of 10MHz for the range over bias control current $100{\mu}A$ to 10mA. The range of output current control is four decade. The power dissipation of the CCII+ is 4.5mW at supply voltage of ${\pm}2.5V$.

Electrical Resistivity of Natural Graphite-Fluorine Resin Composite for Bipolar Plates of Phosphoric Acid Fuel Cell(PAFC) Depending on Graphite Particle Size (인산형 연료전지 분리판용 천연흑연-불소수지계 복합재료의 흑연입도에 따른 전기비저항 변화)

  • Lee, Sang-Min;Beak, Un-Gyeong;Kim, Tae-Jin;Roh, Jae-Seung
    • Korean Journal of Materials Research
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    • v.27 no.12
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    • pp.664-671
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    • 2017
  • A composite material was prepared for the bipolar plates of phosphoric acid fuel cells(PAFC) by hot pressing a flake type natural graphite powder as a filler material and a fluorine resin as a binder. Average particle sizes of the powders were 610.3, 401.6, 99.5, and $37.7{\mu}m$. The density of the composite increased from 2.25 to $2.72g/cm^3$ as the graphite size increased from 37.7 to $610.3{\mu}m$. The anisotropy ratio of the composite increased from 1.8 to 490.9 as the graphite size increased. The flexural strength of the composite decreased from 15.60 to 8.94MPa as the graphite size increased. The porosity and the resistivity of the composite showed the same tendencies, and decreased as the graphite size increased. The lowest resistivity and porosity of the composite were $1.99{\times}10^{-3}{\Omega}cm$ and 2.02 %, respectively, when the graphite size was $401.6{\mu}m$. The flexural strength of the composite was 10.3MPa when the graphite size was $401.6{\mu}m$. The lowest resistance to electron mobility was well correlated with the composite with lowest porosity. It was possible the flaky large graphite particles survive after the hot pressing process.

Comparison Study of Polymer and Ti Sol-Gel Carbon Coating on Ti for PEMFC Bipolar Plates (고분자전해질 연료전지용 Ti 분리판을 위한 고분자와 Ti Sol-Gel 탄소코팅의 비교 연구)

  • Won-Seog Yang;Jae-Ho Lee;Hee-Suk Roh;Ju-Hyun Yoo;Chul-Min Park;Su-Yeon Lee;Sung-Mo Moon
    • Corrosion Science and Technology
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    • v.22 no.6
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    • pp.447-456
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    • 2023
  • In this work, we performed a comparative study examining two coatings on Ti Gr.1 for use in fuel cell bipolar plates. The coatings consisted of carbon black as the conductor along with acrylic polymer and Ti Sol-Gel binder as the binder. Ti Sol-Gel that had precipitated as TiO2 in areas impregnated between carbon black gaps, thereby acting as a binder for carbon black and serving as a polymer coating. Neither of the coatings peeled off during the 90° bend test to check formability. The contact resistance of the TiO2 coating was found to be lower than that of the polymer binder coating. Moreover, due to coating shrinkage (denser) that occurred during the heat treatment process, the TiO2 binder coating showed almost the same level of corrosion resistance, as measured by potentiostatic and EIS tests, despite being thinner than the polymer coating. However, both the polymer binder coating and the TiO2 binder coating had many pores and irregularities internally (around 10 ~ 100 nm) and on the surface (0.1 ~ 2 ㎛). We considered that these pores and irregularities contributed to the lower corrosion resistance.

Temperature Stable Current Source Using Simple Self-Bias Circuit

  • Choi, Jin-Ho
    • Journal of information and communication convergence engineering
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    • v.7 no.2
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    • pp.215-218
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    • 2009
  • In this paper, temperature stable current and voltage references using simple CMOS bias circuit are proposed. To obtain temperature stable characteristics of bias circuit a bandgap reference concept is used in a conventional circuit. The parasitic bipolar transistors or MOS transistors having different threshold voltage are required in a bandgap reference. Thereby the chip area increase or the extra CMOS process is required compared to a standard CMOS process. The proposed reference circuit can be integrated on a single chip by a standard CMOS process without the extra CMOS process. From the simulation results, the reference current variation is less than ${\pm}$0.44% over a temperature range from - $20^{\circ}C$ to $80^{\circ}C$. And the voltage variation is from - 0.02% to 0.1%.

Design and Fabrication of Teletext Bit Slicer IC (Teletext Bit Slicer 집적회로의 설계 및 제작)

  • 申明澈;張榮旭;金永生;高鎭秀;明贊奎;閔聖基
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.3
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    • pp.384-388
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    • 1986
  • This paper describes the design and fabrication of an integrated circuit that can detect the teletext signal included in a composite video signal. The circuit that is based on the comparatorlevel sampling method can detect a stable data signal even from an external circuit with large variation. It has been fabricated by the SST bipolar standard process. Its chip size is $2.5x3.78mm^2$.

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Design of HALL effect integrated circuit with reduced wolgate offset in silicon bipolar technology (옵셋전압을 저감시킨 실리콘 바이폴라 홀 IC 설계)

  • 김정언;홍창희
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.1
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    • pp.138-145
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    • 1995
  • The offset voltage in silicon Hall plates is mainly caused by stress and strain in package, and by alignment in process. The offset voltage is appeared random for condition change with time in the factory, is non-linearly changed with temperature. In this paper proposed new method of design of Hall IC, and methematicaly proved relation layout of chip of 90$^{\circ}$-shift-current Hall plate pair is matched with "Differentail to single ended Conversion amplifier." In the experiment, the offset voltage is reduced about 1/100 time than the original offset voltage.

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Design and Fabrication of SYNC Signal Separator IC (동기신호 분리용 집적회로의 설계 및 제거)

  • 장영욱;김영생;갑명철
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.24 no.6
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    • pp.992-997
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    • 1987
  • This paper describes the design and fabrication of an integrated circuit that can separate the horizontal SYNC., vertical SYNC. and composite SYNC. signal included in a composite video signal. The circuit that is based on the comparator level samplign method can separate a stable SYNC. signal even from an external circuit with large variation. It has been fabrivated by the SST bipolar process. Its chip size is 1.5x1.5mm\ulcorner As a result, we succeeded in fabrication of IC which satisfied DC characteristics and SYNC. singal separator function.

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