• 센서학회지
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• 제13권3호
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• pp.188-194
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• 2004

With a remarkable advance in CMOS (complimentary metal-oxide-semiconductor) process technology, a variety of vision sensors with signal processing circuits for complicated functions are actively being developed. Especially, as the principles of signal processing in human retina have been revealed, a series of vision chips imitating human retina have been reported. Human retina is able to detect the edge and motion of an object effectively. The edge detection among the several functions of the retina is accomplished by the cells called photoreceptor, horizontal cell and bipolar cell. We designed a CMOS vision chip by modeling cells of the retina as hardwares involved in edge and motion detection. The designed vision chip was fabricated using $0.6{\mu}m$ CMOS process and the characteristics were measured. Having reliable output characteristics, this chip can be used at the input stage for many applications, like targe tracking system, fingerprint recognition system, human-friendly robot system and etc.

• 대한전자공학회논문지
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• 제26권3호
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• pp.8-13
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• 1989

부가성 가우시안 잡음 상황하에서, 미지의 확률 분포를 갖는 양극성 2진 불규칙 수형파 신호의 중요한 파라미터인, 진폭과 위상을 Gauss-Markov 추정기를 사용하여 동시에 추정하므로써 전송된 디지탈 데이타를 복원하였다. 그러나, Gauss-Markov 추정기가 이용되기 위해서는 승산기와 적분기로 구성된 상관기를 사용하여, 수신 신호를 표본화 급수로 변환하고 관측된 데이타 벡타를 얻기 위한 사전 처리단계가 필요하게 됨을 알게 되었다.

• 한국전기전자재료학회논문지
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• 제31권4호
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• pp.208-211
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• 2018

This paper details the design of a 1,200 V class trench gate field stop IGBT (insulated gate bipolar transistor) with a nano gate structure smaller than 1 um. Decreasing the size is important for lowering the cost and increasing the efficiency of power devices because they are high-voltage switching devices, unlike memory devices. Therefore, in this paper, we used a 2-D device and process simulations to maintain a gate width of less than 1 um, and carried out experiments to determine design and process parameters to optimize the core electrical characteristics, such as breakdown voltage and on-state voltage drop. As a result of these experiments, we obtained a wafer resistivity of $45{\Omega}{\cdot}cm$, a drift layer depth of more than 180 um, an N+ buffer resistivity of 0.08, and an N+ buffer thickness of 0.5 um, which are important for maintaining 1,200 V class IGBTs. Specially, it is more important to optimize the resistivity of the wafer than the depth of the drift layer to maintain a high breakdown voltage for these devices.

• 한국전기전자재료학회논문지
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• 제33권6호
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• pp.495-499
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• 2020

Power factor improvement at high temperatures has been a major research topic for the development of skutterudite thermoelectric materials. Here, we attempted to optimize the process parameters for manufacturing skutterudite materials, especially for p-type systems. We focused on the effect of aging time variation to maximize the high-temperature performance of the Ce-filled Fe³CoSb¹² skutterudite system. The optimized aging time was concluded to be a key parameter for the formation of single-phase nanostructures in this p-type skutterudite system. The optimized condition was effective in reducing the bipolar effect at high temperature ranges by increasing the carrier concentration in the p-type system. To confirm the conclusions, the electrical conductivity, Seebeck coefficient, and power factor were measured. The results matched well with the microstructure and with those of an XRD analysis performed for the system.

• 한국전기전자재료학회논문지
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• 제22권10호
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• pp.801-807
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• 2009

In this paper, we propose a novel shoot-through protection circuit and pulse generator for half-bridge driver IC. We designed a robust half-bridge driver IC over a variation of processes and power supplies. The proposed circuit is composed a delay circuit using a beta-multiplier reference. The proposed circuit has a lower variation rate of dead time and pulse-width over variation of processes and supply voltages than the conventional circuit. Especially, the proposed circuit has more excellent pulse-width matching of set and reset signals than the conventional circuit. Also, the proposed pulse generator is prevented from fault operations using a logic gate. Dead time and pulse-width of the proposed circuit are typical 250 ns, respectively. The variation ratio is 68%(170 ns) of maximum over variation of processes and supply voltages. The proposed circuit is designed using $1\;{\mu}m$ 650 V BCD (Bipolar, CMOS, DMOS) process parameter, and the simulations are carried out using Spectre simulator of Cadence corporation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.286-287
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• 2012

Reset-first resistive switching mechanism based on reduction reaction in HfO2-x with oxygen drift-diffusion was studied. we first report that the indirect evidence of local filamentary conductive path formation in bulk HfO2 film with local TiOx region at Ti top electrode formed during forming process and presence of anion-migration at interface between electrode and HfO2 during resistive switching through high resolution transmission electron microscopy (HRTEM), electron disperse x-ray (EDX), and electron energy loss spectroscopy (EELS) mapping. Based on forming process mechanism, we expected that redox reaction from Ti/HfO2 to TiOx/HfO2-x was responsible for an increase of initial current with increasing the post-annealing process. First-reset resistive switching in above $350^{\circ}C$ annealed Ti/HfO2 film was exhibited and the redox phenomenon from Ti/HfO2 to TiOx/HfO2-x was observed with high angle annular dark field (HAADF) - scanning transmission electron microscopy (STEM), EDX and x-ray photoelectron spectroscopy. Therefore, we demonstrated that the migration of oxygen ions at interface region under external electrical bias contributed to bipolar resistive switching behavior.

• Journal of electromagnetic engineering and science
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• 제6권2호
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• pp.92-97
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• 2006

In this paper, a fully integrated Ku-band tripler differential MMIC voltage controlled oscillator(VCO), which consists of a differential VCO core and two triplers, is developed using high linearity InGaP/GaAs HBT technology. The VCO core generates an oscillation frequency of 3.583 GHz, an output power of 3.65 dBm, and a phase noise of -96.7 dBc/Hz at 100 kHz offset with a current consumption of 30 mA at a supply voltage of 2.9 V. The tripler shows excellent side band rejection of 23 dBc at 3 V and 12 mA. The tripler differential MMIC VCO produces an oscillation frequency of 10.75 GHz, an output power of -13 dBm and a phase noise of -89.35 dBc/Hz at 100 kHz offset.

• ETRI Journal
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• 제27권5호
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• pp.569-578
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• 2005

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on-chip 1 to 6 GHz up-conversion and 1 to 8 GHz down-conversion mixers using a 0.8 mm SiGe hetero-junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up-conversion mixer was implemented on-chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up-conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down-conversion mixer was implemented on-chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down-conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.

• 전기전자학회논문지
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• 제15권1호
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• pp.37-42
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• 2011

본 논문에서는 0.35 um BCD 공정을 통한 고내압 BCD 소자와 새로운 구조의 BCD 소자를 제작하여 전기적 특성을 분석하였다. 20 V급 BJT 소자, 30/60 V급 HV-CMOS, 40/60 V급 LDMOS 소자의 전기적 특성을 분석하고, 동일 공정을 통해 높은 전류 이득을 갖는 수직/수평형 NPN BJT와 고내압 특성의 LIGBT 소자를 제안하였다. 제안된 수직/수평형 NPN BJT의 항복전압은 15 V, 전류이득은 100으로 측정되었으며, 고내압 특성의 LIGBT의 항복전압은 195 V, 문턱전압은 1.5 V, Vce,sat은 1.65 V로 측정 되었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 The IMAPS-Korea Workshop 2001 Emerging Technology on packaging
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• pp.157-160
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• 2001

APF optical link용 receiver를 하나의 바이폴라 칩으로 실현하기 위하여 수신파장 영역에서 고속.고감도 특성을 갖는 바이폴라 집적용 Si photodiode를 에피 두게 6$\mu\textrm{m}$(epi06)와 12$\mu\textrm{m}$(epi12)로 제작하고 이의 전기.광학적 특성을 조사하였다. 제작된 소자의 전기.광학적 특성을 -5 V의 동작전압에서 측정한 결과, 6 $\mu\textrm{m}$ 에피두께의 경우 접합커패시턴스와 암전류가 각각 4.8 pF와 2.6 pA로 나타났으며, 광신호 전류와 감도특성은 670 nm의 중심파장을 갖는 3.15 ㎼의 입사광 전력 아래에서 각각 0.568 $\mu\textrm{A}$와 0.18 A/W로 나타났다. 에피층의 두께가 12 $\mu\textrm{m}$의 경우 접합커패시턴스와 암전류는 각각 9.8 pF와 171.3 pA로 나타났으며, 광신호 전류와 감도특성은 3.679$\mu\textrm{A}$와 1.17 A/W로 나타났다. 제작된 두 소자는 적색 파장(λ$_{p}$=670nm)부근에서 최대 spectral response(λ$_{p}$=600nm at epi06, λ$_{p}$=700nm at epi12)를 보이고 있다.이고 있다.