• Nuclear Engineering and Technology
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• 제56권1호
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• pp.189-194
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• 2024

This paper presents a radiation-hardened-by-design preamplifier that utilizes a self-compensation technique with a charge-sensitive amplifier (CSA) and replica for total ionizing dose (TID) effects. The CSA consists of an operational amplifier (OPAMP) with a 6-bit binary weighted current source (BWCS) and feedback network. The replica circuit is utilized to compensate for the TID effects of the CSA. Two comparators can detect the operating point of the replica OPAMP and generate appropriate signals to control the switches of the BWCS. The proposed preamplifier was fabricated using a general-purpose complementary metal-oxide-silicon field effect transistor 0.18 ㎛ process and verified through a test up to 230 kGy (SiO₂) at a rate of 10.46 kGy (SiO₂)/h. The code of the BWCS control circuit varied with the total radiation dose. During the verification test, the initial value of the digital code was 39, and a final value of 30 was observed. Furthermore, the preamplifier output exhibited a maximum variation error of 2.39%, while the maximum rise-time error was 1.96%. A minimum signal-to-noise ratio of 49.64 dB was measured.

• Transactions on Electrical and Electronic Materials
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• 제10권2호
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• pp.44-48
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• 2009

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.