• 한국전기전자재료학회논문지
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• 제16권11호
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• pp.1019-1022
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• 2003

We studied the nematic liquid crystal (NLC) aligning capabilities using the new alignment material of a-C:H thin film as working gas at 30W rf bias condition. A high pretilt angle of about 5$^{\circ}$ by ion beam(IB) exposure on the a-C:H thin film surface was measured. A good LC alignment by the IB alignment method on the a-C:H thin film surface was observed at annealing temperature of 250$^{\circ}C$, and the alignment defect of the NLC was observed above annealing temperature of 300$^{\circ}C$. Consequently, the high LC pretilt angle and the good thermal stability of LC alignment by the IB alignment method on the a-C:H thin film surface as working gas at 30W rf bias condition can be achieved.

• 한국군사과학기술학회지
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• 제12권2호
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• pp.222-227
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• 2009

The bias characteristics due to the changes of temperature and temperature gradient of fiber coil are investigated in fiber-optic gyroscope. The bias performance is degraded with the changes of temperature and temperature gradient of fiber coil. The temperature compensation using both the temperature-dependent bias measurement and the temperature-induced error model of fiber-optic gyroscope improves the bias stability about 3 times as much as the uncompensated original case, which leads to very stable bias performance over the temperature range from $-35^{\circ}C$ to $+77^{\circ}C$.

• Journal of Advanced Marine Engineering and Technology
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• 제32권8호
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• pp.1263-1268
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• 2008

In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.

• 대한임상검사과학회지
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• 제45권1호
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• pp.5-8
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• 2013

In the specimen of free PSA in the low concentration, the result in % bias from our institution and comparable evaluation institution was -33.7% which is exceeded % bias ${\pm}20%$ ; however, it was the domestically allowable limit recommended by the laboratory accreditation commission for specimen at the low concentration. In this paper, the cause was accredited by instability of free PSA substance within the specimen, and the specimen stability test was performed according to CLSI documents GP29-A2. After the low and high concentration specimen were made, and rapidly cooled down in a deep freezer with $-30^{\circ}C$, serum of two concentrations was measured for 10 consecutive days with 3 times a day by Architect i2000 and observed a change in the mean value. As the results of two groups, there were changes in the established target value, and a change level was evaluated by calculating it with % bias. The low concentration specimen had no significant reduction until the 4 day lapse in cold storage. However, % bias were reduced by -17.5% from the 5 day lapse, by 21.5% after the 7 day lapse, and by -26.9% after the 9 day lapse. The frozen specimen had only intra-day variation for 10 days. In the high concentration specimen, bias began to show as -12.2% from the 3 day lapse in cold storage. There was reduction by -28.9% from the 5 day lapse, by -39% after the 7 day lapse, and by -42.9% after the 9 day lapse. In the frozen specimen, there was only intra-day variation like the low concentration specimen in cold storage.

• Journal of Electrical Engineering and Technology
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• 제7권4호
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• pp.626-635
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• 2012

Most of single frequency GPS receivers utilize low-quality crystal oscillators. If a lowquality crystal oscillator is utilized as the time reference of a GPS receiver, the receiver's clock bias grows very fast due to its inherent low precision and poor stability. To prevent the clock bias becoming too large, large clock jumps are intentionally injected to the clock bias and the time offset for clock steering purpose. The abrupt changes in the clock bias and the time offset, if not properly considered, induce serious accuracy degradation in relative differential positioning. To prevent the accuracy degradation, this paper proposes an efficient and systematic method to eliminate the undesirable clock jump effects. Experiment results based on real measurements verify the effectiveness of the propose method.

• ETRI Journal
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• 제34권6호
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• pp.966-969
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• 2012

From a practical viewpoint, the topic of electrical stability in oxide thin-film transistors (TFTs) has attracted strong interest from researchers. Positive bias stress and constant current stress tests on indium-gallium-zinc-oxide (IGZO)-TFTs have revealed that an IGZO-TFT with a larger Ga portion has stronger stability, which is closely related with the strong binding of O atoms, as determined from an X-ray photoelectron spectroscopy analysis.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.391-391
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• 2010

The stability enhancement of Znic oxide thin film transistor deposited by PLD-DBD has been reported here using the bias temperature stress test. Znic oxide (ZnO) thin films were deposited on $SiO_2$/Si (100) by pulsed laser deposition method with and without dielectric barrier discharge (DBD) method. The DBD is the efficient method to adopt the nitrogen ions into the thin films. The TFT characteristics of ZnO TFTs with and without Nirogen (N) doping show similar results with $I_{on/off}$ of $10^5{\sim}10^6$. However. the bias temperature stress (BTS) test of N-doped ZnO TFT with DBD shows higher stability than that of ZnO TFT.

• 마이크로전자및패키징학회지
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• 제12권2호
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• pp.105-109
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• 2005

본 논문은 LTCC 공정에 기반을 둔 GSM/DCS dual band 의 소형화된 antenna switch module을 공정변수 따른 특성의 왜곡을 안정화시키는 연구를 수행하였다. 특히 tape thickness의 변화에 따라 패턴간의 기생 커플링이 주된 변수로 작용한다. 두께 50um인 tape으로 제작된 시편의 사이즈는 $4.5{\times}3.2{\times}0.8 mm^3$이고 insertion loss는 Rx mode와 Tx mode 각각 ldB. 1.2dB 이하이다. 공정상에서 tape thickness의 변화에 따라 개발된 모듈의 특성 안정성을 검증하기 위해 각 블록-다이플렉서,필터, 바이어스 회로-을 probing method을 이용, 측정하였고, 각 블록간의 상호관계는 VSWR을 계산하여 비교하였다. 또한 회로적 관점에서 특성 개선을 위해 바이어스 회로부분의 집중소자형과 분포소자형을 구현하여 서로 비교 분석하였다. 이를 통해 각 블록의 측정과 계산된 VSWR의 데이터는 공정변수에 의해 변화된 전체 module의 특성과 안정성 거동을 파악하는데 좋은 정보를 준다. Tape thickness변화에도 불구하고 다이플렉스의 matching값은 연결되는 바이어스 회로와 LPF의 matching값과 상대 matching이 되면서, 낮은 VSWR을 유지하여 전체 insertion loss가 안정화되는 것을 확인하였다. 더불어 분포소자형 바이어스 회로보다는 집중소자형이 다른 회로블럭과의 관계에서 더 좋은 매칭을 이루어 loss개선에 일조하였다. Tape thickness가 6 um이상의 변화를 가져와도 집중소자형 바이어스 회로는 낮은 손실을 유지하여 더 넓은 안정 범위를 가져오기 때문에 양산에 적합한 구조가 될 수 있다 그리고, probing method에 의한 안정성 특성 추출은 세라믹에 임베디드된 수동회로들의 개발에 충분히 적용될 수 있다.

• Transactions on Electrical and Electronic Materials
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• 제12권5호
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• pp.197-199
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• 2011

In this paper, the bottom-gate thin-film transistors (TFTs) were fabricated with an amorphous/microcrystalline Si double layer (DL) as an active layer and the variations of the electrical characteristics were investigated according to the DC bias stresses. Since the fabrication process of DL TFTs was identical to that of the conventional amorphous Si (a-Si) TFTs, it creates no additional manufacturing cost. Moreover, the amorphous/microcrystalline Si DL could possibly improve stability and mass production efficiency. Although the field effect mobility of the typical DL TFTs is similar to that of a-Si TFTs, the DL TFTs had a higher reliability with respect to the direct current (DC) bias stresses.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1243-1246
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• 2009

A novel a-Si TFT integrated gate driver circuit which suppresses the threshold voltage shift due to prolonged positive gate bias to pull-down TFTs, is reported. Negative gate-to-drain bias is applied alternately to the pull-down TFTs to recover the threshold voltage shift. Consequently, the stability of the circuit has been improved considerably.