• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1178-1181
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• 2006

We fabricated a flexible OTFT(organic thin film transistor) backplane for the electrophoretic display. The backplane was composed of $128{\times}96pixels$ on the Polyethylene Naphthalate substrate in which each pixel had one OTFT. The OTFTs employed bottom contact structure and used the cross-linked polyvinylphenol for gate insulator and pentacene for active layer

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.159-161
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• 2007

We fabricated flexible OTFT-backplanes for the electrophoretic display(EPD). The OTFTs employed bottom contact structure on PEN substrate and used the cross-linked polyvinylphenol for gate insulator, pentacene for active layer. Especially, we used PVA/Acryl double layers for passivation of backplane as well as for pixel dielectric layer between backplane and EPD panel. The OTFT-EPD panel worked successfully anddemonstrated to display some patterns.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5B
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• pp.809-815
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• 2010

This paper proposes the structures and algorithms for the adaptive equalizer that are required to allow high speed signaling over 40 Gb/s across a backplane channel. The proposed adaptive DFE has a fast convergence and low computational complexity. Simulations with a 40 Gb/s show that our adaptive equalizer can meet the IEEE 802.3ba requirement for backplane strip line up to 40 inches.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.1-8
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• 2008

We fabricated flexible electrophoretic display(EPD) driven by organic thin film transistors(OTFTs) on plastic substrate. We designed the W/L of OTFT to be 15, considering EPD's transient characteristics. The OTFTs employed bottom contact structure and used Al for gate electrode, the cross-linked polyvinylphenol for gate insulator, pentacene for active layer. The plastic substrate was coated by PVP barrier layer in order to remove the islands which were formed after pre-shrinkage process and caused the electrical short between bottom scan and top data metal lines. Pentacene active layer was confined within the gate electrodes so that the off current was controlled and reduced by gate electrodes. Especially, PVA/Acryl double layers were inserted between EPD panel and OTFT-backplane in order to protect OTFT-backplane from the damages created by lamination process of EPD panel on the backplane and also accommodate pixel electrodes through via holes. From the OTFT-backplane the mobility was $0.21cm^2/V.s$, Ion/Ioff current ratio $10^5$. The OTFT-EPD panel worked successfully and demonstrated to display some patterns.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.50-57
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• 2007

A 5Gbps CMOS　adaptive feed-forward equalizer designed for backplane applications is described. The equalizer has adaptive feedback circuits to control the compensating gain of the equalizing filter, which uses a phase detector in clock recovery circuit to detect ISI (Inter-Symbol Interference) level. This makes the equalizer operate adaptively for a various channel length of backplane environments.

• Aerospace Engineering and Technology
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• v.10 no.1
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• pp.136-140
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• 2011

In this study, thermal model for backplane of GPS antenna in Low Earth Orbit Satellite is updated and orbit thermal analysis is performed. The analysis is focused on the safehold mode of satellite. During the safehold mode, the solar panel is constantly looking to the Sun, and there is not a mission maneuvering. Therefore, antenna backplane receives the maximum heat influx considering the End-Of-Life condition. To maintain the temperature of antenna within allowable limits, radiating tape is applied and its area is determined. Besides, to verify the lowest temperature of the antenna, cold case with Begin-Of-Life analysis is also performed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.300-311
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• 2016

The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.27 no.3
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• pp.15-23
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• 2019

This paper contains analyses and development processes of the requirements to detect the possible intermittent failure in an old avionics backplane. Interconnections for signal transmission between electronic components, such as Pin-to-PCB, FPCB-to-FPCB, pin-to-FPCB, and pint-to-wire, were selected as the main cause of intermittent failure by analyzing target equipment and documents. The possibility of detecting intermittent failures occurring in the target equipment is verified by physics-of-failure analyses. In order to verify the occurrence of intermittent failures and their detectability, latching continuity circuit testers were manufactured and accelerated life tests were performed by applying temperature and vibration cycle in consideration of flight conditions. Through the above process, the detection requirements for the major intermittent failure in the target avionics backplane was developed.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.275-278
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• 2000

As the operating frequency of digital modules in network system becomes fast, integrity of signals between modules is regarded as a important factor in high speed system design. To guarantee the signal integrity, many factors that deteriorate quality of signal should be considered. In this paper, we survey many factors which be considered while in designing and imp]ementing the backplane for high speed router and analyze the simulation result and experimental result.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.141-144
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• 2004

A QVGA active-matrix backplane is produced on a 25${\mu}m$ thin plastic substrate. A 4-mask photolithographic process is used. The insulator layer and the semiconductor layer are organic material processed from solution. This backplane is combined with the electrophoretic display effect supplied by SiPix and E ink, resulting in an electronic paper display with a thickness of only 100${\mu}m$. This is world's thinnest active-matrix display ever made.