• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.2
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• pp.91-98
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• 2008

Domestic standard for Korean T-DMB includes MPEG-4 BSAC (Bit Sliced Arithmetic Coding) audio coding that has been established in 2003. This paper presents an implementation and optimization of MPEG-4 BSAC Audio Decoder on ARM926EJ-S processor. Tools and modules of the BSAC audio decoder were implemented with 32-bit fixed point operations. Further optimization was accomplished using ARM926EJ-S Inline Assembly. The optimization was based on the total number of multiplications and MAC (Multiply and Accumulation) operations causing most of core cycles of ARM926EJ-S, and also based on analysis of ARMv5 instructions. The result of optimization was evaluated on the basis of MIPS (Million Instruction per second). Implementation results show that BSAC bitstream at 96kbps can be decoded in real-time at 65MHz CPU clocks.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1045-1048
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• 1999

In this paper, we report on a set of new algorithms to realize a nonlinear compressed-domain video/audio editor that overcomes various realization problems. For efficiency, the underlying algorithm, which uses a central data structure in the form of doubled linked lists, performs soft edits of cut and paste (which, in turn, involves soft implementations of frame type conversion) and addresses problems relating to video/audio synchronization and random access, and decoder buffer control.

• ETRI Journal
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• v.28 no.5
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• pp.664-667
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• 2006

We propose an efficient audio transcoding algorithm that can convert audio streams from terrestrial digital television broadcasting service stations to those for terrestrial digital multimedia broadcasting hand-held receivers. The proposed algorithm avoids the complicated psychoacoustic analysis by calculating the scalefactors of the bit-sliced arithmetic coding encoder directly from the signal-to-noise ratio parameters of the AC-3 decoder. The bit-allocation process is also simplified by cascading the nested distortion control loop. Through subjective evaluation, it is shown that the proposed algorithm provides comparable audio quality to tandem coding but it requires much smaller complexity.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.94-97
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• 2002

A VLSI architecture of an Ogg Vorbis decoder is proposed : which is dedicated to portable audio appliances. Referring to the computational cost analysis of the decoding processes, the LSP (Line Spectrum Pair) process, which takes more than 50% of the total processing time, can be regarded as a bottleneck to achieve realtime processing by embedded Processors. Thus in our decoder a specific hardware architecture is devised for the LSP process so as to be integrated into a single chip together with an ARM7TDMI processor. In addition, in order to reduce the total hardware cost, instead of the floating point arithmetic, the fixed point arithmetic is adopted. The LSP module has been implemented with 9,740 gates by using a Virtual Silicon 0.l5$\mu\textrm{m}$ CMOS technology, which operates at 58.8MHz with the total CPU load reduced by 57%. It is also verified that the use of the fixed point arithmetic does not incur any significant sound distortion.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1123-1126
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• 1999

In this paper, we propose a real-time implementation of the MPEG-1 layer III and MPEG-2 layer III LSF audio decoding system based on OAK DSP Core. In order to solve the problem of resolution, the system has been used floating-point operation and double precision in dequantization module. The size of ROM is reduced by using the Run-length algorithm of reordered index. The subband synthesis filter module is optimized to have low computational complexity in terms of the size of ROM or RAM. To construct a efficient system, we used both the DSP Core and Parser-Huffman decoder which is implemented with VHDL.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.11
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• pp.13-20
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• 2005

For Modern Consumer and Communication Elecronic Devices, Always Error Protecting HW and SW is used. The Core is RS(Reed Solomon) Codec in Galois Field GF($2^8$). Here New 2 to 3 Symbol RS Decoder Design and Encoder design Method using Normalized error position Value is described. Examples are given to show the methods are working well.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.56-61
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• 2000

Silicon semiconductor technology agrees that the number of transistors on a chip will keep growing exponentially, and it is pushing technology toward the System-On-Chip. In SoC Design, Specification at system level is key of success. Executable Specification reduces verification time. This Paper describes the design of IMDCT for MPEG Audio Decoder employing system-level design methodology and Executable Specification Methodology in the VHDL simulator with FLI environment.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.213-215
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• 2000

디지털 신호처리 알고리즘의 구현은 속도나 메모리의 사용측면에서 고정 소수점 구현이 필요하다. 특히, 정수형 연산 프로세서에서는 소프트웨어에 의한 부동 소수점보다는 고정 소수점 구현이 훨씬 성능이 뛰어나다. 디지털 신호처리 알고리즘의 복잡함과 일반 프로세서의 처리능력의 부족으로 이제까지는 신호처리 알고리즘의 실시간 구현을 위하여 대개 전용 프로세서나 디지털 신호처리를 위한 전용 명령어가 하드웨어적으로 구현되어 있는 프로세서를 사용하여 왔다. 하지만 현재 범용 프로세서의 주파수 속도가 빨라짐에 따라 복잡한 디지털 신호처리 알고리즘을 실시간에 처리할 수 있게 되었다. 하지만 정수형 연산 프로세서에서의 부동 소수점 연산은 프로세서에서 실시간 처리에 많은 어려움을 주게 된다. 본 연구에서는 데이터 타입이 고정된 범용 정수형 연산 프로세서(ARM RISC 32bit CPU)를 가지고 부동 소수점 연산 알고리즘을 고정 소수점 연산형으로 바꾸어서 속도측면과 메모리 측면의 성능을 비교해 보았다.

• The Journal of the Acoustical Society of Korea
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• v.26 no.5
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• pp.214-219
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• 2007

This paper proposes a new IFFT(Inverse Fast Fourier Transform) algorithm, which is proper for IMDCT(Inverse Modified Discrete Cosine Transform) of MPEG-2 AAC(Advanced Audio Coding) decoder. The $2^n$(N-point) type IMDCT is the most powerful among many IMDCT algorithms, however it includes IFFT that requires many calculation cycles. The IFFT used in $2^n$(N-point) type IMDCT employ the bit-reverse data arrangement of inputs and N/4-point complex IFFT to reduce the calculation cycles. We devised a new data arrangement method of IFFT input and $N/4^{n+1}$-type IFFT and thus we can reduce multiplication cycles, addition cycles, and ROM size.

• The Journal of the Acoustical Society of Korea
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• v.23 no.8
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• pp.554-561
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• 2004

As the technologies of semiconductor and multimedia communication have been improved. the high-quality video and the multi-channel audio have been highlighted. MPEG Audio Layer 3 decoder has been implemented as a Processor using a standard. Since the synthesis filter of MPEG-1 Audio Layer 3 decoder requires the most outstanding operation in the entire decoder. the synthesis filter that can reduce the amount of operation is needed for the design of the high-speed processor. Therefore, in this paper, the synthesis filter. the most important part of MPEG Audio, is materialized in FPGA using the method of DAULT (distributed arithemetic look-up table). For the design of high-speed synthesis filter, the DAULT method is used instead of a multiplier and a Pipeline structure is used. The Performance improvement by 30% is obtained by additionally making the result of multiplication of data with cosine function into the table. All hardware design of this Paper are described using VHDL (VHIC Hardware Description Language) Active-HDL 6.1 of ALDEC is used for VHDL simulation and Synplify Pro 7.2V is used for Model-sim and synthesis. The corresponding library is materialized by XC4013E and XC4020EX. XC4052XL of XILINX and XACT M1.4 is used for P&R tool. The materialized processor operates from 20MHz to 70MHz.