• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.1
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• pp.7-13
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• 1985

Design techniques for programmable storage/logic arrays(SLA's) with easily testable features are discussed. The easily testable SLA's will be designed by using additional hardware to provide an easy means to set or check the states. These augmented SLA's have the very short universal test sequences such that the test patterns and responses are uniquely determined only by the size of the SLA's independently of the function of them. The types of faluts considered here are single and multiple stuck faults, crosspoint faults, and bridge faults in SLA's. Fault location and reapir of SLA's are also considered.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.14-24
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• 2009

Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.

• KIISE Transactions on Computing Practices
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• v.21 no.7
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• pp.476-481
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• 2015

We have parallelized the cumulative sum (CUSUM) test of NIST's statistical random number test suite in a CUDA environment. Storing random walks in an array instead of in scalar variables eliminates data dependence. The change in data structure makes it possible to apply parallel scans, scatters, and reductions at each stage of the test. In addition, serial data exchanges between CPU and GPU are removed by migrating CPU's tasks to GPU. Finally we have optimized global memory accesses. The overall speedup is 23 times over the sequential version. Our results contribute to improving security of random numbers for cryptographic keys as well as reducing the time for evaluation of randomness.

• Korean Journal of Metals and Materials
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• v.46 no.2
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• pp.80-87
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• 2008

Many researches related to the reliability of Pb-free solder joints with PCB (printed circuit board) surface finish under thermal or vibration stresses are in progress, because the electronics is operating in hash environment. Therefore, it is necessary to assess Pb-free solder joints life with PCB surface finish under thermal and mechanical stresses. We have investigated 4-points bending fatigue lifetime of Pb-free solder joints with OSP (organic solderability preservative) and ENIG (electroless nickel and immersion gold) surface finish. To predict the bending fatigue life of Sn-3.0Ag-0.5Cu solder joints, we use the test coupons mounted 192 BGA (ball grid array) package to be added the thermal stress by conducting thermal shock test, 500, 1,000, 1,500 and 2,000 cycles, respectively. An 4-point bending test is performed in force controlling mode. It is considered that as a failure when the resistance of daisy-chain circuit of test coupons reaches more than $1,000{\Omega}$. Finally, we obtained the solder joints fatigue life with OSP and ENIG surface finish using by Weibull probability distribution.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.1-5
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• 2010

We developed a novel micro-electro mechanical systems (MEMS) test socket using silicon on insulator (SOI) substrate with the cantilever array structure. We designed the round shaped cantilevers with the maximum length of $350{\mu}m$, the maximum width of $200{\mu}m$ and the thickness of $10{\mu}m$ for $650{\mu}m$ pitch for 8 mm x 8 mm area and 121 balls square ball grid array (BGA) packages. The MEMS test socket was fabricated by MEMS technology using metal lift off process and deep reactive ion etching (DRIE) silicon etcher and so on. The MEMS test socket has a simple structure, low production cost, fine pitch, high pin count and rapid prototyping. We verified the performances of the MEMS test sockets such as deflection as a function of the applied force, path resistance between the cantilever and the metal pad and the contact resistance. Fabricated cantilever has 1.3 gf (gram force) at $90{\mu}m$ deflection. Total path resistance was less than $17{\Omega}$. The contact resistance was approximately from 0.7 to $0.75{\Omega}$ for all cantilevers. Therefore the test socket is suitable for BGA integrated circuit (IC) packages tests.

• The Journal of the Acoustical Society of Korea
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• v.39 no.1
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• pp.47-56
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• 2020

The sound source localization technique has various application fields in the era of internet-of-things, for which the probe size becomes critical. The localization methods using the acoustic intensity vector has an advantage of downsizing the layout of the array owing to a small finite-difference error for the short distance between adjacent microphones. In this paper, the acoustic intensity vector and the Time Difference of Arrival (TDoA) method are compared in the viewpoint of the localization error in the far-field. The comparison is made according to the change of spacing between adjacent microphones of the three-dimensional microphone array arranged in a tetrahedral shape. An additional test is conducted in the reverberant field by varying the reverberation time to verify the effectiveness of the methods applied to the actual environments. For estimating the TDoA, the Generalized Cross Correlation-Phase transform (GCC-PHAT) algorithm is adopted in the computation. It is found that the mean localization error of the acoustic intensimetry is 2.9° and that of the GCC-PHAT is 7.3° for T₆₀ = 0.4 s, while the error increases as 9.9°, 13.0° for T₆₀ = 1.0 s, respectively. The data supports that a compact array employing the acoustic intensimetry can localize of the sound source in the actual environment with the moderate reflection conditions.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.10
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• pp.1089-1097
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• 2002

In this paper, the novel shipboard Active Phased Array Antenna(APAA) system for maritime mobile satellite communications is introduced. The antenna uses novel technologies like wide range hybrid tracking, single antenna elements with both of Rx and Tx, asymmetrical array structure, interference isolation between Rx and Tx, and error correction method from frequency scan effect. The antenna has single aperture for both of Rx and Tx with 32 $\times$ 4 two-dimensional array. The antenna has two beams. Its frequencies are 7.25 ~ 7.75 GHz for Rx and 7.9 ~ 8.4 GHz for Tx. The antenna gains are 35.4 dBi for Rx and 35.7 dBi for Tx, those are 54 % of efficiency. The electrically steering ranges are $\pm$35$^{\circ}$ of elevation direction and $\pm$4$^{\circ}$ of azimuth direction. The mechanical control ranges at hybrid tracking capability are continuous 360$^{\circ}$ of azimuth direction and $\pm$10$^{\circ}$ of elevation direction. The antenna has 2.2$^{\circ}$ of 3 dB beamwidth, -14 dB of sidelobe level, and 21 dB of cross-pol suppression. The antenna performance was measured by near field measurement set. Its system performance was tested on the ship motion simulator and with the satellite transponder simulator. The test result showed that its tracking error was within -3 dB from its peak gain under motion condition. The antenna system was tested by real modulated Direct Broadcasting Satellite(DBS) signals to check its communication processing function.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.10
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• pp.144-155
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• 1998

The array weights that will maximize the SNR for any type of noise environment are determined by the function of the antenna design configuration and the directions of receiving target and interference signals. The conventional SLCs(sidelobe cancellers) using the SNR maximization perform worst from the saturation of the receiving system of main channel when the main antenna has pattern with high gain at the arrival angle of strong interference. In this paper, the new SLC is accomplished by using two independent antenna architecture. Main antenna is implemented with adaptive nulling, which is used for rejecting high-power interference primarily. Auxiliary antenna is realized with adaptive array for receiving interference signal to be suppressed completely, which has a characteristics of sufficient gain for every direction. The new SLC is implemented with above both antennas. We show that the new SLC, which consists of the adaptive nulling main antenna and the adaptive array auxiliary antenna, is useful in reducing the effect of strong interference like jammer, because the adaptive nulling at main antenna prevents its receiver and signal processor for saturation by strong interference. The proposed SLC has improved SNR over the conventional SLCs. The improved SNR at sidelobe region is typically more than 7 dB for a given test signal. Moreover, it improves the SNR of about 20 dB under strong interference at mainlobe.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.12
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• pp.5622-5632
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• 2011

This paper presents the simulation design and analysis of Integrated Logistics System(ILS) which is operated by using the AGV(Automated Guided Vehicle). To maximize the operation performances of ILS with AGV, many parameters should be considered such as the number, velocity, and dispatching rule of AGV, part types, scheduling, and buffer sizes. We established the design of experiment in a way of Orthogonal Array in order to consider (1)maximizing the throughput; (2)maximizing the vehicle utilization; (3)minimizing the congestion; and (4)maximizing the Automated Storage and Retrieval System(AS/RS) utilization among various critical factors. Furthermore, we performed the optimization by using the simulation-based analysis and Evolution Strategy(ES). As a result, Orthogonal Array which is conducted far fewer than ES significantly saved not only the time but the same outcome when compared after validation test on the result from the two methods. Therefore, this approach ensures the confidence and provides better process for quick analysis by specifying exact experiment outcome even though it provides small number of experiment.

• Journal of Biomedical Engineering Research
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• v.44 no.6
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• pp.404-413
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• 2023

In this research, we studied the development of a SUS304 microneedle array based on microfabrication technology and the applicability of Parylene-C thin film, a medical polymer material. First of all, four materials commonly used in the field of medical engineering (SUS304, Ti, PMMA, and PEEK) were selected and a 5 ㎛ Parylene-C thin film was deposited. The applicability of Parylene-C coating to each material was confirmed through SEM analysis, contact angle measurement, surface roughness(Ra) measurement, and adhesion test according to ASTM standards for each specimen. Parylene-C thin film was deposited based on chemical vapor deposition (CVD), and a 5 ㎛ Parylene-C deposition process was established through trial and error. Through characteristic experiments to confirm the applicability of Parylene-C, SUS304 material, which is the easiest to apply Parylene-C coating without pretreatment was selected to develop a microneedle array based on CNC micromachining technology. The CNC micromachining process was divided into a total of 5 steps, and a microneedle array consisting of 19 needles with an inner diameter of 200 ㎛, an outer diameter of 400 ㎛, and a height of 1.4 mm was designed and manufactured. Finally, a 5 ㎛ Parylene-C coated microneedle array was developed, which presented future research directions in the field of microneedle-based drug delivery systems.