• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.999-1007
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• 2002

In this paper, the operation of matched filter for searching initial synchronization in direct sequence spread spectrum receiver is studied. The implementation model of the matched filter by HDL (Hardware Description Language) is proposed. The model has an architecture based on parallelism and pipeline for fast processing, which includes circular buffer, multiplier, adder, and code look-up table. The performance of the model is analyzed and compared with the implementation by a conventional digital signal processor. It is implemented on a FPGA (Field Programmable Gate Array) and its operation is validated in a timing simulation result.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10a
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• pp.469-471
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• 1999

컴포넌트 기반 개발 방법이 확산됨에 따라 소프트웨어 아키텍처는 핵심 기술중의 하나로서 각광받고 있다. 컴포넌트 기반의 아키텍처의 연구와 함께 정형적 아키텍처 기술을 지원하는 많은 아키텍처 기술 언어들이 제시되었다. 그러나, 메시지 전달 패러다임을 기술하고 분석할 필요가 있는 분산 시스템의 경우 기존의 아키텍처 기술 언어들은 이러한 기능의 지원이 부족하다. 본 논문에서는 메시지 전달 패러다임을 명확하게 기술할 수 있고, 이를 기반으로 적합성을 검사할 수 있으며, 일반 개발자들이 이용하기 편리한 시각적 아키텍처 기술 언어를 제시한다. 이를 통하여 분산 시스템을 설계하는 경우, 좀 더 정확한 분석과 정보를 제공할 수 있고, 시각적 언어로서 일반 개발자들이 좀 더 편리하게 아키텍처를 설계할 수 있게 된다.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.24-27
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• 2011

재구성형 프로세서는 높은 성능과 낮은 전력 소모, 재구성이 가능하다는 점에서 갈수록 높아지는 모바일 및 소형 전자기기 시장의 요구 조건을 충족시키기에 적합한 특성을 가지고 있다. 이 논문에서는 아키텍처 명세 언어인 SoarDL 언어를 확장하여 재구성형 프로세서를 효과적으로 기술할 수 있는 방법과 함께, 이를 바탕으로 재구성형 프로세서를 위한 컴파일러를 생성할 수 있는 방안을 제시한다.

• Journal of KIISE:Software and Applications
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• v.36 no.5
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• pp.411-419
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• 2009

In order to derive hidden Information (concept subsumption, concept satisfiability and realization) of OWL ontologies, a number of OWL reasoners have been introduced. Most of the reasoners were implemented to be based on tableau algorithm. However this approach has certain limitation. This paper presents architecture for Medusa. The Medusa is an extended DL-reasoner for SWRL(Semantic Web Rule Language) reasoning under well-founded semantics with ontologies specified in Description Logic. Description logic based ontology reasoners theoretically explore knowledge representation and its reasoning in concept languages. However these logics are not equipped with rule-based reasoning mechanisms for assertional knowledge base; specifically, rule and facts in logic programming, or interaction of rules and facts with terminology. In order to deal with the enriched reasoning, The Medusa provides combining DL-knowledge base and rule based reasoner. The described prototype uses $Prot{\acute{e}}g{\acute{e}}$ API[1] for controlling communication with the ontology reasoner.

• The Journal of the Korea Contents Association
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• v.3 no.3
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• pp.74-84
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• 2003

The Location Service (LCS) feature which provides the terminal UE’s geographical location information has been important issues in IMT-2000 system. The existing location positioning methods are classified into the cell ID based, OTDOA, and network assisted GPS. In this paper, a new hybrid location positioning method which combine three of these methods is proposed. Then the LCS protocol is developed under SDL (Specification and Description Language) development environment after designing a new LCS system architecture and behavior. This protocol design covers the LCS functional model and signaling procedure, system architecture, primitive and data structure, and process SDL diagrams.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.255-266
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• 2015

In this paper, a low-complexity and low-power soft output multiple input multiple output (MIMO) symbol detector is proposed for mobile devices with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode in single hardware and shows the optimal maximum likelihood (ML) performance. By applying a multi-stage pipeline structure and using a complex multiplier based on the polar-coordinate, the complexity of the proposed architecture is dramatically decreased. Also, by applying a clock-gating scheme to the internal modules for MIMO modes, the power consumption is also reduced. The proposed symbol detector was designed using a hardware description language (HDL) and implemented using a 65nm CMOS standard cell library. With the proposed architecture, the proposed MIMO detector takes up an area of approximately $0.31mm^2$ with 183K equivalent gates and achieves a 150Mbps throughput. Also, the power estimation results show that the proposed MIMO detector can reduce the power consumption by a maximum of 85% for the various test cases.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.6
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• pp.96-103
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• 1999

This paper proposes efficient VLSI architecture for computation of the 1-D discrete wavelet transform (DWT). The proposed VLSI architecture computes the wavelet lowpass and highpass output sequences using the product term anhm, $n,m{\ge}0$, where an and hm denote the imput sequence and the wavelet lowpass filter coefficient, respectively. Whereas the conventional architectures compute the lowpass and highpass output sequences using the product terms anhm and angm, respectively, where gm denotes the wavelet highpass filter coefficient. The proposed architecture is applied to computation of the Daubechies 4-tap wavelet transform using the relationships between the Daubechies wavelet filter coefficients. Performance comparison of various architectures for computation of the 1-D DWT are presented. Note that the proposed architecture does not require extra processing units whereas the conventional architectures need them. Also it is modeled in very high speed integrated circuit hardware description language (VHDL) and simulated to show its functional validity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.420-435
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• 2001

As multimedia technology has rapidly grown recently, many researches to process multimedia data efficiently using general-purpose processors have been studied. In this paper, we proposed multimedia instructions which can process multimedia data effectively, and suggested a processor architecture for those instructions. The processor was described with Verilog-HDL in the behavioral level and simulated with CADENCE$^{TM}$ tool. Proposed multimedia instructions are total 48 instructions which can be classified into 7 groups. Multimedia data have 64-bit format and are processed as parallel subwords of 8-bit 8 bytes, 16-bit 4 half words or 32-bit 2 words. Modeled processor is developed based on the Integer Unit of SPARC V.9. It has five-stage pipeline RISC architecture with Harvard principle.e.

• Korean Institute of Interior Design Journal
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• v.14 no.5 s.52
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• pp.254-261
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• 2005

This paper presents an attempt to develop a visual programming language-based 3D virtual reality authoring tool intended to compose virtual interior space. The rapid development of digital technology and the wide spread of the Intenet have expanded the different uses of virtual reality in a number of applications ranging from interior design to building maintenance. In particular, the construction of cyber spaces based on existing interior spaces is becoming increasingly important. Current research, however, remains at the level of converting 3D models into virtual reality models, despite practitioners' needs for structural space models. Moreover, commercial tools to build virtual reality space have the disadvantage of targeting people who have professional knowledge of computer programs and computer graphics. Accordingly, the 3D virtual reality authoring tool developed in this research - called the VESL system - enables virtual and structural space to be easily composed using intuitive and interactive visual interfaces, which are based on visual programming techniques. The VESL system also provides an XML based semantic description of interior space, to be used to describe interior space information. We anticipate that the virtual reality spaces composed by this system will be of considerable use in the fields of architecture and interior design. Further research issues identified at the end of the research include developing a converter/filter for transforming Internet virtual reality standard language, or VRML, and evaluating the application of the system for practical use.