• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• The KIPS Transactions:PartC
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• v.15C no.5
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• pp.409-418
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• 2008

In this paper, we programed the PPP(Point-to-Point Protocol) used in embedded application environments for Globalstar Satellite Modem. There are number of satellite communication systems such as Orbcomm, Globalstar, Inmarsat and etc. But each satellite data service have provided a communication interface only for their own data links. A data communication link is needed to communicate with Globalstar satellite service. Globalstar communication system uses PPP to establish data communication link, so we implemented the embedded processor based PPP protocol. The user terminal equipment also designed in this paper has various input/output devices and sensors applicable to any user specific application. The proposed PPP program works well with Globalstar data communication link through experimental tests.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.1076-1087
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• 2010

Together with a new advent of embedded processor developed to support specific application area and it evolution, a new research of software development to support the embedded processor and its commercial challenge has been revitalized. Retargetability is typically achieved by providing target machine information, ADL, as input. The ADLs are used to specify processor and memory architectures and generate software toolkit including compiler, simulator, assembler, profiler, and debugger. The EXPRESSION ADL follows a mixed level approach-it can capture both the structure and behavior supporting a natural specification of the programmable architectures consisting of processor cores, coprocessors, and memories. And it was originally designed to capture processor/memory architectures and generate software toolkit to enable compiler-in-the-loop exploration of SoC architecture. In this paper, we designed the class-based ADL based on the EXPRESSION ADL to promote the write-ability, extensibility and verified the validation of grammar. For this works, we defined 6 core classes and generated the EXPRESSION's compiler and simulator through the MIPS R4000 description.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.219-222
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• 2002

There are screw, reciprocating type turbo compressor by structure in an air compressor which is essential equipment on the industrial spot. Recently, the application range of a turbo compressor tend to be wide gradually. And this type of compressor needs high speed rotation of impeller in structure so high ratio gearbox and conventional induction motor driving required. This mechanical system have results of increased moment of inertia and mechanical friction loss. Recent studies of modern turbo compressor have been applied to developing super high speed BLDC motor and driver which remove gearbox that make its size small and mechanical friction loss minimum. To accomodate this tendency, we tried to develope a super high speed motor drive system for 150Hp, 70,000rpm direct drive Turbo compressor using DSP(Digital Signal Processor) and SVPWM(Space Vector Modulation PWM) technique. The results of this specific application show that super high speed driver and controller could be implemented well with digital electronics.

• Journal of KIISE
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• v.44 no.2
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• pp.115-123
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• 2017

A message processor is server software that receives non-realtime messages as well as realtime messages from clients that need to be processed within a deadline. With the recent advances of micro-processor technologies and Linux, the message processor is often implemented in Linux-based multi-core servers and it is important to use cores efficiently to maximize the performance of system in multi-core environments. Numerous research efforts on a real-time scheduler for the efficient utilization of the multi-core environments have been conducted. Typically, though, they have been conducted theoretically or via simulation, making a subsequent real-system application difficult. Moreover, many Linux-based real-time schedulers can only be used in a specific Linux version, or the Linux source code needs to be modified. This paper presents the design of a Linux-based message processor for multi-core environments that maps the threads to the cores at user level. The message processor is implemented through a modification of the traditional RM algorithm that consolidates the real-time messages into certain cores using a first-fit-based bin-packing algorithm; this minimizes the response-time delay of the non-real-time messages, while guaranteeing the violation rate of the real-time messages. To compare the performances, the message processor was implemented using the two multi-core-scheduling algorithms GSN-EDF and P-FP, which are provided by the LITMUS framework. The benchmarking results show that the response-time delay of non-real-time messages in the proposed system was improved up to a maximum of 17% to 18%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.15-25
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• 2005

Embedded systems have a set of tasks to execute. These tasks can be implemented either on application specific hardware or as software running on a specific processor. The design of an embedded system involves the selection of hardware software resources, Partition of tasks into hardware and software, and performance evaluation. An accurate estimation of execution time for extreme cases (best and worst case) is important for hardware/software codesign. A tighter estimation of the execution time bound nay allow the use of a slower processor to execute the code and may help lower the system cost. In this paper, we consider an ARM-based embedded system and developed a tool to estimate the tight boundary of execution time of a task with loop bounds and any additional program path information. The tool we developed is based on an exiting timing analysis tool named 'Cinderella' which currently supports i960 and m68k architectures. We add a module to handle ARM ELF object file, which extracts control flow and debugging information, and a module to handle ARM instruction set so that the new tool can support ARM processor. We validate the tool by comparing the estimated bound of execution time with the run-time execution time measured by ARMulator for a selected bechmark programs.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.6
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• pp.465-476
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• 2005

In this paper, we propose a new dynamic reconfiguration method using application-level checkpointing in a grid computing environment with Cactus and Globus. The existing dynamic reconfiguration methods have been dependent on a specific hardware and operating system. But the proposed method performs a dynamic reconfiguration without supporting specific hardwares and operating systems and, an application is programmed without considering a dynamic reconfiguration. In the proposed method, the job starts with an initial configuration of Computing resources and the job restarts including new resources dynamically found at run-time. The proposed method determines whether to include the newly found idle sites by considering processor performance and available memory of the sites. Our method writes the intermediate results of the job on the disks using system-independent application-level checkpointing for real-time visualization during the job runs. After reconfiguring idle sites and idle processors newly found, the job resumes using checkpointing files. The proposed dynamic reconfiguration method is proved to be valid by decreasing total execution time In K*Grid.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.6
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• pp.99-105
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• 2022

This paper deals with the problem of appropriately allocating multiple processors arriving at the ready queue to the block in the user space of the main memory is divided into blocks of variable size at compilation time. The existing allocation methods, first fit(FF), best fit(BF), worst fit(WF), and next fit(NF) methods, had the disadvantage of waiting for a specific processor because they failed to allocate all processors arriving at the ready queue. The proposed algorithm in this paper is a simple block packing algorithm that allocates as many processors as possible to the largest block by sorting the size of the partitioned blocks(holes) and the size of the processor in the ready queue in descending order. The application of the proposed algorithm to nine benchmarking experimental data showed the performance of allocating all processors while having minimal internal fragment(IF) for all eight data except one data in which the weiting processor occurs due to partition errors.

• Electronics and Telecommunications Trends
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• v.24 no.6
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• pp.94-98
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• 2009

최근 모바일 멀티미디어 기기들의 사용이 증가하면서 고성능 멀티미디어 프로세서에 대한 필요성이 높아지고 있는 추세이다. DSP 기반의 시스템은 범용성에 기인하여 다양한 응용 분야에서 사용될 수 있으나 주문형반도체 보다 높은 가격과 전력소모 그리고 낮은 성능을 가진다. ASIP는 주문형반도체의 저비용, 저전력, 고성능과 범용 프로세서의 유연성이 결합된 새로운 형태의 프로세서로서, 단일 칩 상에 H.264, VC-1, AVS, MPEG 등과 같은 다양한 멀티미디어 비디오 표준 및 OFDM과 같은 통신 시스템을 지원하고 또한 고성능의 처리율과 계산량을 요구하는 차세대 비디오 표준의 구현을 위한 효과적인 해결책으로 주목되고 있다. 본 기술 문서에서는 ASIP의 특징과 애플리케이션의 가속 방법, ASIP을 위한 컴파일러 설계 및 응용에 관하여 기술한다.