• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• The Magazine of the IEIE
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• v.31 no.8
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• pp.44-51
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• 2004

최근 SoC (System on Chip) 기술의 발전으로 최대 10 Gbps의 처리율을 갖는 네트워크 프로세서가 개발되고 있다. 네트워크 프로세서는 기존의 ASIC (Application Specific Integrated circuit)또는 FPGA (Field Programmable Gate Array) 등 하드웨어가 수행하던 고속의 패킷 처리 기능을 소프트웨어 기반으로 처리하도록 함으로써 다양한 기능의 패킷 처리를 저비용으로 단시간 내에 개발 할 수 있는 장점을 갖고 있다.(중략)

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2351-2357
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• 2010

Recently, USN technology has been spreaded to all areas of application systems. In addition to urban application systems such as u-City, u-Home and u-Education, u-Farming(ubiquitous farming) technology supports agricultural innovations in the farm. In the u-farming environment for livestock or plant production, key environmental factors i.e. temperature, humidity and luminosity are to be set optimally to increase productivity and safety by applying USN technology. This approach could change agricultural environment. In this paper, we proposed an implantable micro sensor node to be implanted into laying hen to monitor deep body temperature. This sensor node uses SoC(System-on-Chip) designed for USN. In addition to that, we discussed about further considerations on the practical use of proposed sensor node.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.5
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• pp.1139-1144
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• 2008

In this paper, we propose an automatic generation method of transaction level(TL) model from algorithmic model to verify system specification fast and effectively using virtual platform. The TL virtual platform including structural properties such as timing, synchronization and real-time is one of the effective verification frameworks. However, whenever change system specification or HW/SW mapping, we must rebuild virtual platform and additional design/verification time is required. And the manual description is very time-consuming and error-prone process. To solve these problems, we build TL library which consists of basic components of virtual platform such as CPU, memory, timer. We developed a set of design/verification tools in order to generate a virtual platform automatically. Our tools generate a virtual platform which consists of embedded real-time operating system (RTOS) and hardware components from an algorithmic modeling. And for communication between HW and SW, memory map and device drivers are generated. The effectiveness of our proposed framework has been successfully verified with a Joint Photographic Expert Group (JPEG) and H.264 algorithm. We claim that our approach enables us to generate an application specific virtual platform $100x{\tims}1000x$ faster than manual designs. Also, we can refine an initial platform incrementally to find a better HW/SW mapping. Furthermore, application software can be concurrently designed and optimized as well as RTOS by the generated virtual platform

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2731-2740
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• 2012

ASIC(application specific integrated circuit) process is a set of various technologies for fabricating a chip. Generally there have been many researches for RTL design, synthesis, floor plan & routing, low power scheme, clock tree synthesis, and testability which are widely researched in recent. In this paper we propose a new methodology of power strap routing in basis of design experience and experiment. First the power strap for vertical VDD and VSS and horizontal VDD and VSS is routed, and then after the problems which are generated in this process are analyzed, we propose a new process for resolving them. For this, the strap guide is inserted to protect the unnecessary strap routing and dumped for next steps. Next the unnecessary power straps which are generated the first inserting process are removed, and the pre-routing is performed for the macro cells. Finally the resultant power straps are routed using the dumped routing guide. Through the proposed process we identified the efficient and stable route of the power straps.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.4
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• pp.178-184
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• 2005

In this paper, using diplexer structure and varactor diode controlled by reverse bias voltage for diplexer switch gives possibilities to improve isolation and current characteristics. 1 have newly designed switch with high isolation by application varactor diode corresponding to capacitor of diplexer. The low-pass filter for proposed tunable diplexer passes the microwave signal in the bandwidth for wireless cellular network systems and high-pass filter passes it in the bandwidth for wireless personal communication services (PCS) network systems. As the capacitance of the low-pass filter increases, the cut-off frequency can be moved to low frequency, so that the switch is on state in cellular bandwidth and off state in the PCS bandwidth, in contrast to, as the capacitance for attenuation characteristic of high-pass filter increases, it can be moved to high frequency, so that the switch is off state and on state in the cellular bandwidth. it is possible to improve isolation and current consumption characteristics by application diplexer design methods and varactor diode. 1 expect that the tunable diplexer circuit and design methods should be able to find applications on MMIC and low temperature copired ceramic (LTCC).

• Proceedings of the Korean Geotechical Society Conference
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• 2009.09a
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• pp.745-751
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• 2009

The anchor is used extensively for a cutting slope, an earth retaining wall, an uplift resistance of sub-structures and so on at civil engineering projects and is classified by aim in use, tendon material, and ground/tension fixing type. It can be distinguished extensively into friction type, bearing type, and complex type by ground fixing type. Generally, bond length of friction type anchor has application to 3~10m depending on the friction-resistance characteristics. In this study, 'DEW(double enlargement wedge) bearing type anchor' of new concept is devised. The bond length is about 0.6~0.8m. It can be used on the ground to have the strength characteristics above it of weathered rock. There are merits which are 'period reduction' and 'cost saving' through the minimum of the boring length. In addition, it is so called environmentally friendly Methods because it can reduce the quantity of carbon dioxide through the reducing drilling machine operation time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.

• Korean Chemical Engineering Research
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• v.58 no.3
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• pp.498-498
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• 2020

• Journal of the Korea institute for structural maintenance and inspection
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• v.8 no.4
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• pp.223-230
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• 2004

It is growing the application of the removal ground anchor with tension force for earth retaining constructions in the downtown. Nowadays, we can find the compression dispersion anchor on many site. But, it is occur some probelems in behabior of anchors because of impossible to tense p.c strand uniformly with existing equipment due to different length of p.c strand. So we tried to tense each p.c strand uniformly with auto back equipment in-situ test. This study compared and analyzed apply to elastic theory in-situ test results of an existing equipment with those of auto back equipment. As a result of the test, It has been proved that differences of tension force in the existing equipment increases with increasing the number of p.c strand. This can cause an ultimate failure of the concentrated p.c strand and a shear failure of ground. So it has been proved that auto back equipment is necessary.