• Journal of Information Display
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• v.6 no.4
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• pp.11-15
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• 2005

We propose a current mode logic circuit design method for LTPS TFT for enhancing circuit operating speed. Current mode inverter/buffers with passive resistive load had been designed and fabricated. Measurement results indicated that the smaller logic swing of the current mode allowed significantly faster operation than the static CMOS. In order to reduce the chip size, both all pTFT and all nTFT active load current mode inverter/buffer had been designed and analyzed by HSPICE simulation. Even though the active load current mode circuits were inferior to the passive load circuits, it was superior to static CMOS gates.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.4
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• pp.261-266
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• 2018

When the clamp meter approaches the electric path where current is flowing, leakage current can be measured at a distance from the electric current because the induced current increases as the magnitude of the current increases and approaches nearer to the electric path. Therefore, measurements were carried out from a distance to avoid this effect. In addition, the measured values differ depending on the location of the power line that penetrates the ZCT of the clamp meter, thus measurements were performed at a location where this effect was minimized. The fraction of compliant branch circuits, whose leakage current was lower than 1.00 mA, was found to be 69.0% out of the total of 439 branch circuits, while the percentage of compliant branch circuits having an insulation resistance higher than $0.20M{\Omega}$ was found to be 93.2%. The reason why the percentage of compliant branch circuits with low leakage current was low might be due to the inclusion of capacitive leakage current in the total measured leakage current.

• Journal of information and communication convergence engineering
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• v.15 no.4
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• pp.237-243
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• 2017

This paper presents an analysis of the electromagnetic interference of a heterogeneous power bus where electromagnetic bandgap (EBG) cells are irregularly arranged. To mitigate electrical-noise coupling between high-speed circuits, the EBG structure is placed between parallel plate waveguide (PPW)-based power buses on which the noise source and victim circuits are mounted. We examine a noise suppression characteristic of the heterogeneous power bus in terms of scattering parameters. The characteristics of the dispersion and scattering parameters are compared in the sensitivity analysis of the EBG structure. Electric field distributions at significant frequencies are thoroughly examined using electromagnetic simulation based on a finite element method (FEM). The noise suppression characteristics of the heterogeneous power bus are demonstrated experimentally. The heterogeneous power bus achieves significant reduction of electrical-noise coupling compared to the homogeneous power buses that are adopted in conventional high-speed circuit design. In addition, the measurements show good agreement with the FEM simulation results.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.231-234
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• 1989

In recent, due to the advanced development of the power semiconductor devices, the Digital Simulation becomes essential in order to investigate the behavior of the system before the manufacturing of the system by using computer for design and analysis of Power Electronic systems. This paper develope the program so-called PECA, which can be applied for the Power Electronic circuits composing of power transistors, thyristers, GTOs and power FET, etc. We consider transistor DC chopper circuit and prove the effectiveness of our program by both the experiment and simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.1
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• pp.68-72
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• 2013

The series connection-type superconducting fault current limiter (SFCL) with two magnetically coupled circuits was suggested and its effectiveness through the analysis on the current limiting and recovery characteristics was described. The fault current limiting characteristics of the proposed SFCL as well as the load voltage sag compensating characteristics according to the winding direction were investigated. To confirm the fault current limiting and the voltage sag suppressing characteristics of the this SFCL, the short-circuit tests for the simulated power system with the series connection-type SFCL were carried out. The series connection-type SFCL designed with the additive polarity winding was shown to perform more effective fault current limiting and load voltage sag compensating operations through the fast quench occurrence right after the fault appears and the fast recovery operation after the fault removes than that with the subtractive polarity winding.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.11a
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• pp.93-96
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• 1993

BiCMOS technology, which combines CMOS and bipolar technology, offers the possibility of achieving both very high density and high performance. In this paper, the characteristics of BiCMOS and CMOS circuits, especilly the delay time is studied. BiCMOS inverter, which has high drive ability because of bipolar transistor, drives high load capacitance and has low-power characteristics because the current flows only during switching transient just like the CMOS gate. BiCMOS inverter has the less dependence on load capacitance than CMOS inverter. SPICE that has been used for electronic circuit analysis is chosen to simulate these circuits and the characteristics is discussed.

• Publications of The Korean Astronomical Society
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• v.13 no.1 s.14
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• pp.123-128
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• 1998

The Blandford-Znajek process, which extracts the rotational energy of the supermassive black hole at the center of an active galactic nucleus, is now well explained and educated through the electronic circuit analysis established by Macdonald and Thorne. The Macdonald-Thorne circuits consist of the batteries and resistances of the central black hole and the astrophysical region around the accretion disk. In this letter we will consider the possibility whether we can connect coils and condensers in such circuits or not. If possible, that may explain a sudden corona-phenomenon in an active galactic nucleus. We conclude that a flash of order $\~5\times10^{40}\;ergs\;s^{-1}$ can occur around a $\~10^9M_\bigodot$ black hole through this process.

• Journal of Sensor Science and Technology
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• v.28 no.1
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• pp.17-22
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• 2019

As CMOS technology scales down, reliability is becoming an important concern for VLSI designers. This paper analyzes gate-oxide breakdowns (i.e., the time-dependent dielectric-breakdown (TDDB) aging effect) as a reliability issue for combinational circuits with 45-nm technology. This paper shows simulation results for the noise margin, delay, and power using a single inverter-chain circuit, as well as the International Symposium on Circuits and Systems (ISCAS)'85 benchmark circuits. The delay and power variations in the presence of TDDB are also discussed in the paper. Finally, we propose a novel method to compensate for the logic failure due to dielectric breakdowns: We used a higher supply voltage and a negative ground voltage for the circuit. The proposed method was verified using the ISCAS'85 benchmark circuits.

• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.29-33
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• 2021

A 5.8-GHz 1W wireless power transmission system was used for charging a smart phone. The voltage of one RF power receiver with antenna was not enough for charging. Several power receivers for charging a smart phone was connected serially. The voltage of several RF power receivers are highly enough for charging a smart phone within 50cm. However, the lack of current from small capacitances of RF-DC converters is not suitable for charging smart phone. It means very long charging time. In this paper, the voltage multiplier circuits for RF-DC converters were analyzed to increase the current and voltage at the same time to reduce the charging time in smartphone RF wireless charging. Through the analysis of multiplier circuits, the 7-stage parallel multiplier circuit with voltage-doubler units are suitable for charging the smartphone, which supplies 5V and 700mA at 3V@5.8GHz.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.1113-1118
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• 2004

This paper presents the dynamic analysis method for an electromechanical system. The engineer has at his disposal a variety of software simulation tools. However, difficulties arise when the study of the behavior of complex electromechanical systems in combination with coupling element is required. Typical examples of such systems are machines for factory automation, home automation, and office automation. Dynamic systems analysis packages or electronic systems analysis packages offer the restrictive to simulate these mixed systems such electromechanical product. Electronic circuit analysis algorithm is easily incorporated into a multi-body dynamics analysis algorithm. The governing equation of electronic circuit is formulated as a differential algebraic equation form including both electrical and mechanical variables and is simultaneously solved in every time step. This analysis method clearly demonstrates the application potential for mixed electromechanical simulation.