• Proceedings of the IEEK Conference
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• 2002.06c
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• pp.143-146
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• 2002

The aim of this work is the real-time road edge detection using the fast processing of Cellular Analogic Parallel Processing Networks(CAPPN). The CAPPN is composed of 2D analog cell way. If the dynamic programming is implemented with the CAPPN, the optimal path can be detected in parallel manner Provided that fragments of road edge are utilized as the cost inverse(benefit) in the CAPPN-based optimal path algorithm, the CAPPN determines the most plausible path as the road edge line. Benefits of the proposed algorithm are the fast processing and the utilization of optimal technique to determine the road edge lines.

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.1
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• pp.84-91
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• 2005

In this paper, we describe the real-time parallel processing simulator developed for the use of performance analysis of rolling missiles. The real-time parallel processing simulator developed here consists of seeker emulator generating infrared image signal on aircraft, real-time computer, host computer, system unit, and actual equipments such as auto-pilot processor and seeker processor. Software is developed from mathematic models, 6 degree-of-freedom module, aerodynamic module which are resided in real-time computer, and graphic user interface program resided in host computer. The real-time computer consists of six TIC-40 processors connected in parallel. The seeker emulator is designed by using analog circuits coupled with mechanical equipments. The system unit provides interface function to match impedance between the components and processes very small electrical signals. Also real launch unit of missiles is interfaced to simulator through system unit. In order to apply the real-time parallel processing simulator to performance analysis equipment of rolling missiles it is essential to perform the performance verification test of simulator.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1019-1022
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• 2003

This paper has proposed a 4- bit 20MHz Flash A/D converter design available analog signal processing and realized its intergrated circuit. The parallel comparison method A/D converter quantized analog signals swiftly using various converters. Also this theme has designed economic power dissipation circuit using a preamplifier of low volt & power CMOS comparator. Also the system was fabricated by Hynix 0.35um CMOS process.

• 전기의세계
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• v.26 no.1
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• pp.87-90
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• 1977

Various simulation techniques were developed in the modeling of biological system during the last decades. Mostly analog and hybrid simulation techniques have been used. The authors chose the Digital Analog Simulation (DAS) technique by using the MIMIC language to simulate the saccadic eye movement system performances on the digital computer. There have been various models presented by many investigators after Young & Stark's sampled-data model. The eye movement model chosen by the authors is Robinson's model III which shows the parallel information processing characteristics clearly to the double-step input stimuli. In the process of simulation, the parameter and constants used were based on the neurophysiological data of the human and animals. The analog model blocks were converted to the corresponding MIMIC block diagrams and programmed into the MIMIC statements. The program was run on the CDC Cyber 72-14 computer. The essential input stimulus was double-step of 5 and 10 degrees, and target durations chosen were 50,100 and 150 msec. The results obtained by the DAS technqiue were in good agreement with analog simulation carried out by other investigators as well as with the experimental human saccadic eye movement responses to double-step target movements.

• Journal of the Korea Society of Computer and Information
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• v.11 no.4 s.42
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• pp.35-45
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• 2006

RIn this paper. we describe real-time parallel processing simulator developed for the use of performance analysis of rolling missiles. The real-time parallel processing simulator developed here consists of seeker emulator generating infrared image signal on aircraft, real-time computer, host computer, system unit, and actual equipments such as auto-pilot processor and seeker processor. Software is developed according to the design requirements of mathematic model, 6 degree-of-freedom module, aerodynamic module which are resided in real-time computer. and graphic user interface program resided in host computer. The real-time computer consists of six TI C-40 processors connected in parallel. The seeker emulator is designed by using analog circuits coupled with mechanical equipments. The system unit provides interface function to match impedance between the components and processes very small electrical signals. Also real launch unit of missiles is interfaced to simulator through system unit. In order to use the real-time parallel processing simulator developed here as a performance analysis equipment for rolling missiles, we perform verification test through experimental results in the field.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.9
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• pp.540-546
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• 2003

A fast pattern classification algorithm with Cellular Nonlinear Network-based dynamic programming is proposed. The Cellular Nonlinear Networks is an analog parallel processing architecture and the dynamic programing is an efficient computation algorithm for optimization problem. Combining merits of these two technologies, fast pattern classification with optimization is formed. On such CNN-based dynamic programming, if exemplars and test patterns are presented as the goals and the start positions, respectively, the optimal paths from test patterns to their closest exemplars are found. Such paths are utilized as aggregating keys for the classification. The algorithm is similar to the conventional neural network-based method in the use of the exemplar patterns but quite different in the use of the most likely path finding of the dynamic programming. The pattern classification is performed well regardless of degree of the nonlinearity in class borders.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.5
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• pp.493-502
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• 2009

In this paper, we compare the performance of initial timing acquisition in direct sequence ultra-wideband(DS-UWB) systems with different transmit pulse shaping filters through extensive computer simulations. Simulation results show that the timing acquisition performance of the DS-UWB system, whose chip rate is 1.32 Gchip/s, employing a rectangular transmit filter is similar to that employing a square root raised cosine(SRRC) filter with an interpolation factor of 4 in the realistic UWB channels(CM1 and CM3) as well as the additive white Gaussian noise(AWGN) channel. Additionally, we present both a 24-parallel digital correlator structure and a 24-parallel processing searcher operating at a 55 MHz system clock, and then briefly discuss the initial timing acquisition procedure. Because we can adopt an 1.32 Gsample/s digital-to-analog(D/A) converter and an 1.32 Gsample/s analog-to-digital(AID) converter in the DS-UWB system by employing the rectangular transmit filter, we have a realistic solution for the DS-UWB chipset development.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.1
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• pp.49-56
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• 1994

This paper describes the design principles and methods of electronic processor for thermal imager with the SPRITE detector, operating in the 8-12 micron band. The thermal imager consists of a optical scanner containing the detector and an electrical signal processor. The optical scanner utilizing rotating polygon and oscillating mirror, is 2-dimensional serial/parallel scan type using 5 elements of the detector. And the electronic processor has pre-processing of 5 chnanel's thermal signal from the detector, and performs digital scan conversion to reform the parallel data stream into serial analog data compatible with conventional RS-170 video. Through the designed electronic processor, we have acquired a satisfactory thermal image. And the MRTD (Minimum Resolvable Temperature Difference) is 0.5$^{\circ}$K at 7.5 cycles/mm.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.285-288
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• 2005

We propose a novel programmable miniature vision module based on a custom designed analog VLSI (aVLSI) chip. The vision module consists of the optical flow vision sensor embedded with commercial off-the-shelves digital hardware; in our case is the Intel XScale PXA270 processor enforced with a programmable gate array device. The aVLSI sensor provides gray-scale imager data as well as smooth optical flow estimates, thus each pixel gives a triplet of information that can be continuously read out as three independent images. The particular computational architecture of the custom designed sensor, which is fully parallel and also analog, allows for efficient real-time estimations of the smooth optical flow. The Intel XScale PXA270 controls the sensor read-out and furthermore allows, together with the programmable gate array, for additional higher level processing of the intensity image and optical flow data. It also provides the necessary standard interface such that the module can be easily programmed and integrated into different vision systems, or even form a complete stand-alone vision system itself. The low power consumption, small size and flexible interface of the proposed vision module suggests that it could be particularly well suited as a vision system in an autonomous robotics platform and especially well suited for educational projects in the robotic sciences.