• 대한전자공학회논문지
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• 제23권6호
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• pp.923-928
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• 1986

This paper describes the design and fabrication of a high performance digital tuning analog component integrated circuit that contains a television station detector and decoders(H and L types). When the comparator level sampling method is used, this integrated circuit can be used as a stable channel selector for an external circuit with very large signal variation. It has been fabricated using the SST bipolar standard process and its chip size is 2.2x2.1mm\ulcorner As a result, we have succeeded in fabricating the IC that satisfies the D.C characteristics, and the channel station detector and decoder function.

• 대한전자공학회논문지
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• 제23권5호
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• pp.605-615
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• 1986

The phase-locked loop(PLL) is a communication receiver which operates as a coherent detector by continuously correcting the phase error. In this paper analysis for the Phase-error behavior of analog phase-locked loop (APLL) in the presence of additive white gaussian noise has been done theoretically and experimentally. A close form solution of the first-order loop is obtained and approximate solutions are derived for the second-order loops with RC, leadlag and perfect integrator filters. The perdormance of APLL's and their characteristics are also thoroughly investigated through experiments. In order to analyze the effect of the stochastic nature on nonlinear dynamics characteristics of the second order APLL, the phase error distribution and its variance have been obtained by using the Fokker-Planck equation. Theoretical results agree closely with those of experiment.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.299-302
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• 1999

An analog implementation of space vector PWM is proposed in this paper. It is shown that a space vector PWM can be implemented by adding a zero sequency voltage to reference voltage of triangle comparison PWM. The proposed scheme is implemented by six diodes and, an operational amplifier circuit and, a few resistors.

• 전자공학회지
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• 제19권6호
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• pp.46-54
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• 1992

• 전자공학회지
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• 제12권4호
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• pp.32-37
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• 1985

• ETRI Journal
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• 제32권6호
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• pp.911-920
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• 2010

This paper presents a method of designing hybrid analog/asymmetrical square-root (SR) FIR filters. In addition to the conventional frequency domain constraints, the proposed method considers time-domain constraints as well, including the inter-symbol interference (ISI) and the opening of the eye pattern at the receiver output. This paper also reviews a systematic way to find the discrete-time equivalence of analog parts in a band-limited digital communication system. Thus, a phase equalizer can be easily realized to compensate for the nonlinear phase responses of the analog components. With the hybrid analog/SR FIR filter co-design, examples show that using the proposed method can result in a more robust ISI performance in the presence of the receiver clock jitter.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.847-850
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• 1998

One of the most difficult problem of designing VLSI is a mixed-circuit design, that is to design circuit containing both analog parts and digital parts. Digital to analog converter and analog to digital converter is a typical case. Especially it can be a serious problem when mixed circuit are put into a large digital circuit like microcontroller. However nowadays this problem is settled by separating analog circuit parts outside the IC. This technique is based on converting a digital signal into a pulse sequence. Then an analog signal is obtained by averaging this pulse sequence at the external low-pass filter. An anlog to digital converter is designed using a stochastic logic instead of a traditional PWM (pulse-width modulation) signal and ins implemente dusing FPGa. Stochastic pulse sequence can be made as a simple circuits and moreover can be mathematically processed by simple circuits -AND gates. The spectral property of stochastic pulse sequence method is better than that of PWM method. So it make easy to design a external low-pass filter. This technique has important advantages, especially the reduction of the ADC cost.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1003-1006
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• 2003

본 논문에서는 sub-micron 소자에서 SCE(Short Channel Effect) 억제를 위한 Halo 와 SSR(Super Steep Retrograde Well) 적용에 따른 analog 특성의 열화를 석하고 이를 개선하기 위해 Twist 이온주입과 In, Sb Halo 를 채택하였다. Analog 특성은 CMOS 의 amplifier 과 Comparator 로의 사용을 고려해 Drain Rout과 Early voltage를 이용해 나타내었으며 Digital 성능을 함께 고려하였다. 실험결과 NMOS 의 경우 45 twist Halo 조건에서, PMOS의 경우 As보다 Sb를 Halo 로 적용하는 경우 더 우수한 analog 특성을 나타내었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.93-96
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• 2001

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.

• 한국산학기술학회논문지
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• 제10권2호
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• pp.248-255
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• 2009

통신시스템에서의 에러의 처리는 매우 중요한 문제로서 비터비 디코더와 같은 에러처리를 위해서 주로 절대값으로 표현하기 때문에 아날로그 절대값 회로가 자주 필요하게 된다. 이 논문에서는 절대값을 정확하게 계산할 수 있는 아날로그 절대값 회로를 제안하였다. 제안한 절대값 회로에는 부호가 반대인 두 신호들을 만든 다음, 이 신호들을 아날로그MAX회로에 인가하여 둘 중 최대값을 출력하게 하는 방법이다. 이 구조를 회로로 구현하기 위해서는 두 개의 입력 신호를 반대방향으로 차를 구하여, 크기는 같고 부호가 다른 두 개의 신호를 만든 다음 이들을 MAX회로의 입력으로 사용하는 회로를 설계하였다. 본 논문에서는 제안한 회로를 Hspice를 이용하여 시뮬레이션을 수행했으며, 그 결과를 제시하였다.