• ETRI Journal
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• v.32 no.1
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• pp.154-156
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• 2010

Oscillation-based testing of analog-to-digital converters represents a viable option for low-cost built-in self-testing in mixed-signal design. While numerous papers have addressed implementation issues, little attention has been paid to the measurement accuracy. In this letter, we highlight an inherent measurement uncertainty which has to be considered when deriving the parameters from the oscillation frequency.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.129-131
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• 2000

A new analog synchronous mirror delay to be used in the wide-bandwidth clocking circuits is proposed to overcome the frequency dependency of the negative-delay values in the conventional analog synchronous mirror delay. The scheme adopts a new dummy-delay compensation technique by adopting the comparator with inherent systematic offset to achieve the enhanced negative-delay range especially prominent at high frequency applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.269-274
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• 2004

Current delivery system, in which the analog current produced by a unique DAC circuit is stored into a current-memory circuit and delivered in a time-divided sequence, shows variation of output current as low as 4% in a current source data-driver IC for AM-OLED driven by a current-programmed method without any fuse repairing after fabrication. This driver IC has 54 outputs and can sink constant current as low as 3 ${\mu}A$ with 6-bit analog levels. Such a low current level without variation can hardly be obtained by an ordinary MOS transistor because the current level is in the sub-threshold region and changes exponentially with threshold voltage variation. Thus we adopted a current mirror circuit composed of bipolar transistors to supply well-controlled current within a nano-ampere range.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.168-173
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• 2004

A low power CMOS receiver baseband analog circuit based on alternating filter and gain stage is reported. For the given specifications of the baseband analog block, optimum allocation of the gain, IIP3 and NF of the each block was performed to minimize current consumption. The fully integrated receiver BBA chain is fabricated in $0.18\;{\mu}m$ CMOS technology and IIP3 of 30 dBm with a gain of 55 dB and noise figure of 31 dB are obtained at 4.86 mW power consumption.

• ETRI Journal
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• v.29 no.4
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• pp.536-538
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• 2007

We propose and describe the fabrication of a linear power amplifier (LPA) using a new analog feedforward method for the IMT-2000 frequency band (2,110-2,170 MHz). The proposed analog feedforward circuit, which operates without a pilot tone or a microprocessor, is a small and simple structure. When the output power of the fabricated LPA is about 44 dBm for a two-tone input signal in the IMT-2000 frequency band, the magnitude of the intermodulation signals is below -60 dBc and the power efficiency is about 7%. In comparison to the fabricated main amplifier, the magnitude of the third intermodulation signal decreases over 24 dB in the IMT-2000 frequency band.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.32-41
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• 1996

We propose the improved GMSK (gaussian-filtered minimum shift keying) quadrature modulator using the FIR(finite impulse response )filter whose coefficients are obtained form the differnce of phase response, and design its ASIC (applicaton specific integrated circuit) which can be used for GSM (global system for mobile communication) digital cellular system and DCS 1800 (digital cellular system at 1800MHz) personal communication system. Input data become quantized I and Q channel 10 bit signal through cosine and sine ROM mapping after being filtered by the FIR filter whose normalized bandwidth is 0.3 and designed by considering intersymbol interference as well as sampling ratio. These two signals become the GMSK modulated I and Q channel signal through DAC (digital-to-analog converter) and 7th order analog chebyshev LPF(low pass filter) respectively. The difference between the ideal analog signal and its digitized signal is analyzed in terms of sampling noise, quantization noise, truncation noise and coefficient noise. And the effect of the LPF following the DAC is considered. The ASIC design of the GMSK quadrature modulator is also confirmed by an experiment.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.6
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• pp.94-103
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• 1997

This paper presents motor speed and revolution angle detection method using a sinusoidal AC tacho-generator. The 2-phase or 3-phase output tacho-generator can be adopted, and its' output voltages must have sinusoidal waveforms. Because the detection algorithm is simple, the proosed method can be implemented with analog devices or microprocessor conveniently. And the proposed method has a very short detection delay time. Especially in the analog implementation, there is no delay time without the settling time of analog devices. With the experimental results, it is verified that the proposed method can acculately detect the instantaneous motor speed and revolution angle over the wide ranges.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.3
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• pp.1-5
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• 1983

The effects of modal noise of analog video transmission systems using semiconductor laser diode is investigated. The system linearity degradation due to modal noise is examined for various fiber types. It was concluded that in alalog video transmission systems using multimode fiber, modal noise is so serious that reduction of coherency is essential to the development and that single mode libers are adequate for high quality analog video transmission systems.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.135-139
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• 1996

It is difficult to fabricate precise resistors for the analog integrated circuits using MOS technology. Until now polysilicon resistors were used at the analog integrated circuits, but some deviations of resistance and sensitive variation processes still cause their misactions. In order to improve these misactions, we suggest a CMOS resistor cell which provides precise resistance and excellant linearity. Also we designed the second order active low pass filter using the CMOS resistor cells and verified their superior performances compared to the actual resistors.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.465-466
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• 2006

In this paper, novel analog duty cycle corrector (DCC) with a digital duty error detector is proposed. The digital duty error detector measures the duty error of the clock and converts it into a digital code. This digital code is then used to accurately correct the duty ratio by adaptively steering the charge-pump current. The proposed duty cycle corrector was implemented using an 80nm DRAM process with 1.8V supply voltage. The simulation result shows that the proposed duty cycle corrector improves the settling time up to $70{\sim}80%$ at 500MHz clock frequency for the same duty correction accuracy as the conventional analog DCC.