• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.119-128
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• 2004

In this paper, a low-power 8-point DCT structure is proposed using add and shift operations. Proposed structure adopts 4 cycles for complete 8-point DCT in order to minimize size of hardware and to enable high-speed processing. In the structure, hardware for the first cycle can be shared in the next 3 cycles since all columns in the DCT coefficient matrix are common except sign. Conventional DCT structures implemented with only add and shift operation use CSD(Canonic Signed Digit) form coefficients to reduce the number of adders. To reduce the number of adders further, we propose a new structure using common sub-expression sharing techniques. With this techniques, the proposed 8-point DCT structure achieves 19.5% adder reduction comparison to the conventional structure using only CSD coefficient form.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.283-290
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• 2004

In this paper, a low-power structure for 512 tap FIR filter in MPEG audio algorithm is proposed. By using CSD(Canonic Signed Digit) form filter coefficients and maximum sharing of input signal sample, it is shown that the number of adders of proposed structure can be minimized. To minimize the number of adders, the proposed structure utilizes the 4 steps of sharing, i.e., common input sharing, linear phase symmetric filter coefficient sharing, block sharing for common input, and common sub-expression sharing. Through Verilog-HDL coding, it is shown that reduction rates in the implementation area and relative power consumption of the proposed structure are 60.3% and 93.9% respectively, comparison to those of the conventional multiplier structure.

• ETRI Journal
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• v.33 no.5
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• pp.695-703
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• 2011

The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.

• ETRI Journal
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• v.35 no.4
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• pp.697-705
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• 2013

Emerging trends in the area of digital very large scale integration (VLSI) signal processing can lead to a reduction in the cost of the cochlear implant. Digital signal processing algorithms are repetitively used in speech processors for filtering and encoding operations. The critical paths in these algorithms limit the performance of the speech processors. These algorithms must be transformed to accommodate processors designed to be high speed and have less area and low power. This can be realized by basing the design of the auditory filter banks for the processors on digital VLSI signal processing concepts. By applying a folding algorithm to the second-order digital gammatone filter (GTF), the number of multipliers is reduced from five to one and the number of adders is reduced from three to one, without changing the characteristics of the filter. Folded second-order filter sections are cascaded with three similar structures to realize the eighth-order digital GTF whose response is a close match to the human cochlea response. The silicon area is reduced from twenty to four multipliers and from twelve to four adders by using the folding architecture.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.289-293
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• 2008

In this paper, we propose the hardware architecture to accelerate 2D Vector graphics process for mobile devices. we propose the Transformation Unit Architecture that considerates the operation dependency. It has 3 cycles excution time and uses 2 multipliers and 2 adders. Proposed paint generation unit uses a LUT method, so it does not execute color interpolation which needs to be calculated every time. The proposed OpenVG 1.0 Accelerator achieved a 2.85 times faster performance in a tiger model.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.157-160
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• 2002

This paper proposed a guideline for selecting the arithmetic circuit architecture. The guideline incorpo-rates the new concept of PDSP (power-delay-size product) and the weighting method. HSPICE simulations havc been performed to several full adders in order to prove the validity of the proposed guideline. We applied this guideline to select an optimized FA (full adder) architecture and successfully implemented the DAC's digital blocks.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.337-340
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• 2001

This paper presented a new structure of RSA cryptosystem using modified Montgomery algorithm and CSA(Carry Save Adder) tree. Montgomery algorithm was modified to a radix-4 modified Booth algorithm. By appling radix-4 modified Booth algorithm and CSA tree to modular multiplication, a clock cycle for modular multiplication has been reduced to (n＋3)/2 and carry propagation has been removed from the cell structure of modular multiplier. That is, the connection efficiency of full adders is enhanced.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1748-1751
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• 2002

An expression for the average carry propagation delay in a ripple carry adder is obtained which is exact up to terms of the order 0(n$\^$-1/ln n). The case of several adders working in parallel is also considered.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.04a
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• pp.177-180
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• 1986

A high performance Butterfly Arithmetic Unit for FFT processor using two adders is proposed in this papers, which is Based on the distributed and merged arithmetic. Due to simple and easy architecture to implement, this proposed processor is well suited to systolic FFT processor. Simulation was performance using YSLOG (Yonsei logic simulator) on IBM AT computer, to verify logic. By using 3um double Metal CMOS technology,Butterfly arithmetic have been achieved in 1.2 usec.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.657-660
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• 2000

This paper proposes a Data-Flow-Graph (DFG) restructuring to reduce calculating errors in loop folding scheduling. The prime cause of calculating error is rounding errors due to the restriction of the operation digit of functional units. This rounding error is increased more by using multipliers than adders, so reducing the number of multiplications and putting off them as much as possible reduce rounding errors. The proposed approach reduces the number of multiplications by restructuring DFG in loop folding.