• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.543-545
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• 2017

This paper describes the SAO hardware architecture design for high performance in-loop filters. SAO is an inner module of in-loop filter, which compensates for information loss caused by block-based image compression and quantization. However, HEVC's SAO requires a high computation time because it performs pixel-unit operations. Therefore, the SAO hardware architecture proposed in this paper is based on a $4{\times}4$ block operation and a 2-stage pipeline structure for high-speed operation. The information generation and offset computation structure for SAO computation is designed in a parallel structure to minimize computation time. The proposed hardware architecture was designed with Verilog HDL and synthesized with TSMC chip process 130nm and 65nm cell library. The proposed hardware design achieved a maximum frequency of 476MHz yielding 163k gates and 312.5MHz yielding 193.6k gates on the 130nm and 65nm processes respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.401-404
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• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.15 no.3
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• pp.3-12
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• 2005

This paper introduces a 3D perceptual model based on JND(Just Noticeable Difference) and proposes a video watermarking scheme which is perceptual approach of adaptive embedding in 3D-DCT domain. Videos are composed of consecutive frames with many similar adjacent frames. If a watermark is embedded in the period of similar frames with little motion, it can be easily noticed by human eyes. Therefore, for the transparency the watermark should be embedded into some places where motions exist and for the robustness its magnitude needs to be adjusted properly. For the transparency and the robustness, watermark based on 3D perceptual model is utilized. That is. the sensitivities from the 3D-DCT quantization are derived based on 3D perceptual model, and the sensitivities of the regions having more local motion than global motion are adjusted. Then the watermark is embedded into visually significant coefficients in proportion to the strength of motion in 3D-DCT domain. Experimental results show that the proposed scheme improves the robustness to MPEG compression and temporal attacks by about $3{\sim}9\%$, compared to the existing 3D-DCT based method. In terms of PSNR, the proposed method is similar to the existing method, but JND guarantees the transparency of watermark.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.6
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• pp.115-121
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• 2013

This paper related with the DSE-MMA (Dithered Sign-Error MMA) that is the simplification of computational arithmetic number in blind equalization algorithm in order to compensates the intersymbol interference which occurs the passing the nonlinear communication channel in the presence of the band limit and phase distortion. The SE-MMA algorithm has a merit of H/W implementation for the possible to reduction of computational arithmetic number using the 1 bit quantizer in stead of multiplication in the updating the equalizer tap weight. But it degradates the overall blind equalization algorithm performance by the information loss at the quantization process compare to the MMA. The DSE-MMA which implements the dithered signed-error concepts by using the dither signal before qualtization are added to MMA, then the improved SNR performance which represents the roburstness of equalization algorithm are obtained. It has a concurrently compensation capability of the amplitude and phase distortion due to intersymbol interference like as the SE-MMA and MMA algorithm. The paper uses the equalizer output signal, residual isi, MD, MSE learning curve and SER curve for the performance index of blind equalization algorithm, and the computer simulation were performed in order to compare the SE-MMA and DSE-MMA applying the same performance index. As a result of simulation, the DSE-MMA can improving the roburstness and the value of every performance index after steady state than the SE-MMA, and confirmed that the DSE-MMA has slow convergence speed which meaning the reaching the seady state from initial state of adaptive equalization filter.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.26-39
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• 2007

In recent years, rate control is an important technique in real time video communication applications using H.264/AVC. Many existing rate control algorithms employ the quadratic rate-distortion model, which is determine the target bits for each P frame. In this paper, a new rate control algorithm for transmission of H.264/AVC video bit stream through CBR(Constant Bit Rate) channel is proposed. The proposed algorithm predicts an adaptive QP(Quantization Parameter) for improving video distortion, due to high motion and abruptly scene change, which target bit rate and MAD(Mean of Absolute Difference) for current frame considering image complexity variance between previous and current frames. Additionally, it uses frame skip technique to maintain bit stream within a manageable range and protect buffer from overflow or underflow. Experimental results show that the proposed method gives a quality improvement of about 0.5dB when compared to previous rate control algorithm. Also our proposed algorithm encodes the video sequences with less frame skipping compared to the existing rate control for H.264/AVC.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.1
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• pp.9-18
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• 2004

This paper presents an efficient image compression method for memory reduction in multimedia processor which can be simply implemented in hardware and provides high performance. The multimedia processor, which includes processing of high-resolution images and videos, requires large memories: they are external frame memories to store frames and internal line memories for implementing some linear filters. If we can reduce those memories by adopting a simple compression method in multimedia processor, it will strengthen its cost competitiveness. There exist many standards for efficiently compressing images and videos. However, those standards are too complex for our purpose and most of them are 2-D block-based methods, which do not support raster scanned input and output. In this paper, we propose a low-complexity compression method which has good performance, can be implemented with simple hardware logic, and supports raster scan. We have adopted 1${\times}$8 Hadamard transform for simple implementation in hardware and compression efficiency. After analyzing the coefficients, we applied an adaptive thresholding and quantization. We provide some simulation results to analyze its performance and compare with the existing methods. We also provide its hardware implementation results and discuss about cost reduction effects when applied in implementing a multimedia processor.