• Proceedings of the KIPE Conference
• /
• 2008.06a
• /
• pp.277-279
• /
• 2008

In this paper, a novel active boost converter for SR drive is proposed. An active capacitor circuit is added in the front-end. Based on this active capacitor network, when boost switch turns off, this network seems as passive capacitor network. And the voltage of boost capacitor can keep balance with dc-link voltage automatically. In the capacitor network, discharging voltage is general dc-link voltage in parallel-connected capacitors; charging voltage is double dc-link voltage in series-connected capacitors. When boost switch turns on, two capacitors are connected in series, and discharging voltage is up to double dc-link voltage. So the fast excitation current can be obtained from this mode. Profit from fast excitation and fast demagnetization mode, the performance and output power can be improved. Some computer simulations are done to verify the performance of proposed converter.

• Proceedings of the KIPE Conference
• /
• 2008.06a
• /
• pp.505-507
• /
• 2008

A conventional active-clamp forward (ACF) converter is a favorable candidate in low-to-medium power applications. However, the switches suffer from high voltage stress, i.e., sum of the input voltage and the reset capacitor voltage. Therefore, it is not suitable for high input voltage applications such as a front-end converter of which the input voltage is about 400-$V_{dc}$. To solve this problem, three-switch ACF (TS-ACF) converter, which employs two main switches and one auxiliary switch with low voltage stress, is proposed. Utilizing low-voltage rated switches, the proposed converter is promising for high input voltage applications with high efficiency and low cost.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.52 no.4
• /
• pp.148-153
• /
• 2003

In this paper, the low voltage 3V Sigma-Delta Digital Analog Converter(DAC) is designed for using in the transmitter of ADSL analog front-end. We have developed the CMOS DAC according to ANSI T1.413-2(DMT) standard specifications of the chip. The designed 4th-order DAC is composed of three block which are 1-bit DAC, 1st-order Switched-Capacitor filter and analog active 2nd-order Resistor-Capacitor(RC) filter. The HSPICE simulation of the designed DAC showing 65db SNR, is connected with 1.1MHz continuous lowpass filter. And also, we have performed the circuits verification and layout verification(ERC, DRC, LVS) followed by fabrication using TSMC 2-poly 5-metal p-substrate CMOS $0.35{\mu}m$ processing parameter. Finally, the chip testing has been performed and presented in the results.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.23 no.2
• /
• pp.121-128
• /
• 2018

This work proposes a simple control method of a buck-type active power decoupling circuit that can minimize the ripple values in the dc link voltage. The proposed method utilizes a simplified duty calculation method and an optimal compensation gain tracking algorithm with variable-step approach. Thus, the dc link voltage ripple can be effectively reduced through the proposed method along with rapid response in tracking the optimum compensation gain. Moreover, the proposed method has better dynamic responses in the load fluctuation or abnormal situation. MATLAB/Simulink simulation and hardware-in-the-loop-simulation(HILS)-based experimental results are presented to validate the effectiveness of the proposed control method.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.5 no.2
• /
• pp.61-67
• /
• 2012

In this paper, In this paper, we consider a dynamic range in the frequency converter to obtain a high conversion gain and linearity while operating area proposed to broaden the design. Super-heterodyne RF Front-End style was applied to the active mixer stage, GaAs devices were used. Circuit design easy and simple forms benefit circuit is constructed in the drain mixer, passive mixer with the operating area were compared and analyzed. The simulation results of the conversion gain of 2.4dB and 0.2dBm about a gain-compression point, and showed the dynamic range of 71.9dB, when compared with passive mixers, dynamic range of approximately 6dB improvement was identified. Measurements of an approximately 2dB conversion gain and-1.0dBm of the gain-compression point, and confirmed that the active area of 71.1dB. When compared with passive mixers, dynamic range of is reduced by approximately 8dB has been improved.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.26 no.4
• /
• pp.294-297
• /
• 2021

A grid voltage estimation method for modular plug-in active power decoupling (APD) circuits is proposed in this study as direct replacements of electrolytic capacitors. Since modular plug-in APD circuits cannot have additional grid voltage sensors and should be operated independently without information exchange with the front-end converter, it is impossible to obtain the phase information of the grid directly. Therefore, the proposed method uses the second-order harmonic component of the DC-link voltage to estimate the grid voltage necessary to control the APD circuit. By employing the proposed method, the concept of modular plug-in APD circuits can be realized and implemented without direct detection of the grid voltage. The experimental results based on hardware-in-the-loop simulation (HILS) validate the effectiveness of the proposed control method.

• Journal of Power Electronics
• /
• v.15 no.2
• /
• pp.309-318
• /
• 2015

This study proposes a dual-output single-stage bridgeless single-ended primary-inductor converter (DOSSBS) that can completely remove the front-end full-bridge alternating current-direct current rectifier to accomplish power factor correction for universal line input. Without the need for bridge diodes, the proposed converter has the advantages of low component count and simple structure, and can thus significantly reduce power loss. DOSSBS has two uncommon output ports to provide different voltage levels to loads, instead of using two separate power factor correctors or multi-stage configurations in a single stage. Therefore, this proposed converter is cost-effective and compact. A magnetically coupled inductor is introduced in DOSSBS to replace two separate inductors to decrease volume and cost. Energy stored in the leakage inductance of the coupled inductor can be completely recycled. In each line cycle, the two active switches in DOSSBS are operated in either high-frequency pulse-width modulation pattern or low-frequency rectifying mode for switching loss reduction. A prototype for dealing with an $85-265V_{rms}$ universal line is designed, analyzed, and built. Practical measurements demonstrate the feasibility and functionality of the proposed converter.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.10
• /
• pp.31-39
• /
• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

• Proceedings of the KIPE Conference
• /
• 2017.07a
• /
• pp.212-213
• /
• 2017

In this paper is presented a pre-charging sequence for single-phase cascaded neutal-point-clamped(NPC) converters for capacitors voltage balancing. capacitor imbalance problem in pre-charge sequence is caused in cascaded NPC converter by its topology. the DC link voltage at each NPC converter module can be balanced by the proposed switching method. the design and performance of the proposed sequence are verified by simulation and experimental results using prototype.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.12 no.5
• /
• pp.507-511
• /
• 2019

The use of regenerative energy in AC drive systems has been an issue since the system became an industry standard in the 1990s. According to the quantity of the regenerative energy, the braking resistor in the case of low capacity was common. However the use of such low amount of energy is actively discussed, and the method of mounting the regenerative converter is becoming popular. In this paper, an isolated regenerative converter for reducing the circulating current which is mentioned as the biggest disadvantage of the conventional power regenerative converter system is proposed. In order to save energy, employing a power regenerative converter system for utilizing regenerative energy in an AC drive system is common. However due to the structure of the system, a circulating current is generated, which inevitably causes a decrease in efficiency. In this paper, an isolated regenerative power converter system is proposed to solve the circulating current and computer simulation to verify the possibility. The simulation results show that 20% of the circulating current of the conventional system does not appear in the proposed system, and the validity of the proposed system is confirmed.