• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1196-1198
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• 2005

This paper presents the realization of a four-terminal floating nullor (FTFN), which is simple configuration comprised three OTAs. The external bias currents of the OTAs can electronically adjust the current gain of the proposed FTFN. The realization method is suitable for implementation in monolithic integrated form. To demonstrate the circuit performances, the proposed FTFN was simulated by the use of the PSPICE analog simulation program and implemented using the commercially available OTAs. The simulation and experimental results verifying the performances of the proposed circuit are agreed with the theoretical values. Some application example in the design of the proposed FTFN as electronically tunable active element are also included.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1243-1246
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• 2006

A new source follower circuit for the integrated circuit of AMLCDs is proposed. Active load is added and calibration operation is applied to compensate the circuits. Proposed circuit is capable of minimizing the variation from both timing and device variations through measured results, the uniformity and bias effect are discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.728-735
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• 2016

A 70 MHz temperature-compensated on-chip CMOS relaxation oscillator for mobile display driver ICs is proposed to reduce frequency variations. The proposed oscillator compensates for frequency variation with respect to temperature by adjusting the bias currents to control the change in delay of comparators with temperature. A bandgap reference (BGR) is used to stabilize the bias currents with respect to temperature and supply voltages. Additional temperature compensation for the generated frequency is achieved by optimizing the resistance in the BGR after measuring the output frequency. In addition, a trimming circuit is implemented to reduce frequency variation with respect to process. The proposed relaxation oscillator is fabricated using 45 nm CMOS technology and occupies an active area of $0.15mm^2$. The measured frequency variations with respect to temperature and supply voltages are as follows: (i) ${\pm}0.23%$ for changes in temperature from -30 to $75^{\circ}C$, (ii) ${\pm}0.14%$ for changes in $V_{DD1}$ from 2.2 to 2.8 V, and (iii) ${\pm}1.88%$ for changes in $V_{DD2}$ from 1.05 to 1.15 V.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.26 no.7
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• pp.875-880
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• 2016

A new hybrid permanent magnet biased magnetic levitation actuator (maglev) is developed. This new maglev actuator is composed of two C-core electromagnetic cores separated with two permanent magnets. Compared to the conventional hybrid maglev actuators, the new actuator has unique flux paths such that bias flux paths are separated with control flux paths. The control flux paths have minimum reluctances only developed by air gaps, so the currents to produce control fluxes can be minimized. The gravity load can be compensated with the permanent magnet bias fluxes developed at off-centered air gap positions while external disturbances are controlled with control fluxes by currents. The consumed power to operate this levitation system can be minimized. 1-D magnetic circuit model is developed for this model such that the flux densities and magnetic forces are extensively analyzed. 3-D finite element model is also developed to analyze the performances of the maglev actuator.

• Journal of the Korean Society of Industry Convergence
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• v.22 no.1
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• pp.29-37
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• 2019

A new permanent magnet biased hybrid maglev actuator is developed. Compared to the classical hybrid maglev actuators, the new maglev has unique flux paths such that bias fluxes are separated with control flux paths. The control flux paths have minimum reluctances only developed by air gaps, so the currents to produce control fluxes can be minimized. The consumed power to operate this maglev system can also be minimized. The gravity load can be compensated with the static magnetic forces developed by the permanent magnet bias fluxes while external disturbances are controlled with the bidirectional AC magnetic forces developed by control fluxes by currents. 1-D circuit model is developed for this model such that the flux densities and magnetic forces are extensively analyzed. 3-D finite element model is also developed to analyze the performances of the maglev actuator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.560-566
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• 2004

In this paper, active frequency doubler with broadband characteristics from 6 ㎓ to 12 ㎓ was designed and fabricated using PHEMT. The designed frequency multiplier has a bias point near pinch-off and a proposed series RC circuit between bias line and input matching network far the improvement of stability. With 0 ㏈m input power, second harmonic of 1.7 ㏈m at 12 ㎓ -27.5 ㏈c suppression of 6 ㎓ fundamental, -18 ㏈c suppression of 18 ㎓ 3rd harmonic, and the 3 ㏈ output bandwidth of 1,8 ㎓ have been measured.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.10
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• pp.1025-1033
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• 2002

This paper presents temperature-compensation circuits of Ku-band amplifiers for satellite payload. After carefully investigating design specifications of Ku-band amplifiers for satellite payload, we designed three types or temperature-compensation circuits, which are an active bias circuit, an attenuator control, and an ALC loop circuit. Our design technique demonstrates good agreement between measured and predicted results. These temperature-compensation circuits are suitable for Ku-band satellite payload active components, such as channel amplifiers, LNA and IF amplifiers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.1
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• pp.166-172
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• 2001

A RF wideband receiver for INMARSAT-B satellite communications system was composed of low noise amplifier and high gain amplifier, The low noise amplifier used to the resistive decoupling circuit for input impedance matching and self-bias circuits for low noise. The high gain amplifier consists of matched amplifier type to improve receiver gain. The active bias circuit can be used to provide temperature stability without requiring the large voltage drop or relatively high-dissipated power needed with a bias stabilization resistor. The bandpass filter was used to reduce a spurious level. As a result, the characteristics of the receiver implemented here show more than 60 dB in gain and less than 1.8:1 in input and output voltage standing wave ratio(VSWR), especially the carrier to noise ratio which is input signal level -126.7 dB m at 1537.5 MHz is a 45.23 dB /Hz at a 1.02 kHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1111-1116
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• 2011

In this paper, a 60 GHz bidirectional active phase shifter with 130 nm CMOS is presented by replacing CMOS passive switchs in switched-line type phase shifter with Common Gate Amplifier(bidirectional amplifier). Bidirectional active phase shifter is composed of bidirectional amplifier blocks and passive delay line network blocks. The suitable topology of bidirectional amplifier block is CGA(Common Gate Amplifier) topology and matching circuits of input and output are symmetrical due to design same characteristic of it's forward and reverse way. The direction(forward and reverse way) and amplitude of amplification can be controlled by only one bias voltage($V_{DS}$) using combination bias circuit. And passive delay line network blocks are composed of microstrip line. An 1-bit phase shifter is fabricated by Dongbu HiTek 1P8M 130-nm CMOS technology and simulation results present -3 dB average insertion loss and respectively 90 degree and 180 degree phase shift at 60 GHz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.8
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• pp.1566-1571
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• 2011

The objective of this paper is to present a quantitative analysis leading to the assessment of optimum terminating impedances in the design of active frequency multipliers. A brief analysis of the basic principal of the GaAs FET frequency multiplier is presented. The analysis is outlined in bias optimization and drive power determination. Utilizing the equivalent circuit model of GaAs FET, we have simulated the optimized load impedance for the maximum output of the active frequency multipliers. The C-class and reverse C-class frequency doublers have been fabricated and the load impedances have been measured. The experimental results are in good agreement with the estimated results in the simulation with the accuracy of 90%.