• Title/Summary/Keyword: ATM Switching

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A Fault Tolerant ATM Switch using a Fully Adaptive Self-routing Algorithm -- The Cyclic Banyan Network (완전 적응 자기 경로제어 알고리즘을 사용하는 고장 감내 ATM 스위치 - 사이클릭 베니안 네트웍)

  • 박재현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.9B
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    • pp.1631-1642
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    • 1999
  • In this paper, we propose a new fault tolerant ATM Switch and a new adaptive self-routing scheme used to make the switch to be fault tolerant. It can provide more multiple paths than the related previous switches between an input/output pair of a switch by adding extra links between switching elements in the same stage and extending the self-routing scheme of the Banyan network. Our routing scheme is as simple as that of the banyan network, which is based on the topological relationships among the switching elements (SE’s) that render a packet to the same destination with the regular self-routing. These topological properties of the Banyan network are discovered in this paper. We present an algebraic proof to show the correctness of this scheme, and an analytic reliability analysis to provide quantitative comparisons with other switches, which shows that the new switch is more cost effective than the Banyan network and other augmented MIN’s in terms of the reliability.

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High-Speed, Large-Capacity ATM switching-chip Implemented by MCM Technology (고속 대용량 ATM Switching칩 구현을 위한 MCM기술 적응)

  • 김남우;허창우;임실묵
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.5 no.4
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    • pp.791-797
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    • 2001
  • In this paper, high-speed ,large-capacity ATM switching-chip is developed by MCM technology. MCM technology is suited for light-weight portable communications, mobile computing, high-frequency applications. For test of the developed MCM switching-chips, the simulating model is made by VHDL code of previously developed chip and input-output values of modeling pattern are obtained through the simulation. After the pattern values in chip-test machine are inserted , their results are compared with the simulation results. The design in this paper is simulated by synopsys design tool using SUN workstation and functions of chip is measured by TRILLIUM machine. Simulated and measured results have been compared, showing close agreement. Last, the MCM technique presented in this paper will provide useful insight into future designs.

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Implementation of TMN-based Performance Proxy Agent for ATM Switching Systems (ATM 교환 시스템을 위한 TMN 기반의 Proxy 성능 관리대행자 구현)

  • 권봉경;김화성
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.6C
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    • pp.562-570
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    • 2002
  • The network-wide performance management is crucial for maintaining the quality of network services, which requires the collection and monitoring the performance data at individual network nodes. Most of the public networks, however, are composed of diverse, heterogeneous network nodes that are managed by various types of proprietary management systems with a conventional operator console and embedded management functions, which makes it difficult to implement the integrated performance management systems. Even though the developments of TMN (Telecommunication Management Network) based management systems are being attempted, the little work has been done in performance management area. In this paper, we propose the performance monitoring architecture for ATM switches using the 0₃ object model and describe how to implement the TMN-based performance prosy agent for ATM switching systems. The proposed performance proxy agent provides the TMN standard performance management interfaces by translating the proprietary performance management functions, which eventually leads to network-wide integrated performance management.

Fault Management in Multichannel ATM Switches (다중 채널 ATM 스위치에서의 장애 관리)

  • 오민석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.8A
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    • pp.569-580
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    • 2003
  • One of the important advantages of multichannel switches is the incorporation of inherent fault tolerance into the switching fabric. For example, if a link which belongs to the multichannel group fails, the remaining links can assume responsibility for some of the traffic on the failed link. On the other hand, if faults occur in the switching elements, it can lead to erroneous routing and sequencing in the multichannel switch. We investigate several fault localization algorithms in multichannel crossbar ATM switches with a view to early fault recovery, The optimal algorithm gives the best performance in terms of time to localization but is computationally complex which makes it difficult to implement. We develop an on-line algorithm which is computationally mote efficient than the optimal algorithm. We evaluate its performance through simulation. The simulation results show that performance of the on line algorithm is only slightly sub-optimal for both random and bursty traffic. Finally a fault recovery algorithm is described which utilizes the information provided by the fault localization algorithm.

A Survey and Implementation of UNI Signalling Protocol in ACE64 Switching System (ATM 교환 시스템에서 가입자-망 간 신호 프로토콜 고찰 및 구현)

  • 오문균;한미숙주성
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.309-312
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    • 1998
  • B-ISDN에서 교환 노드로서 동작하게 될 ATM 교환 시스템은 사용자 단말이 ITU-T 신호 권고안을 사용하는 단말과 ATM Forum 신호규격을 사용하는 단말이 공존할 수 있다는 전제하에 모든 신호 프로토콜을 다 수용할 수 있는 호/연결 제어 소프트웨어가 요구된다. 따라서 이 논문에서는 ITU-T 신호 프로토콜과 ATM Forum 신호 프로토콜에 대하여 신호 메세지, 정보 요소, 신호 능력을 비교 검토하여 정리하였다. 이 비교 검토 결과에 따라서 ITU-T 1.2931, 1.2971, ATM Forum UNI3.1 신호 프로토콜을 처리하는 기능 블럭과 UNI4.0 신호프로토콜을 처리하는 기능 블럭을 분리하여 신호 프로토콜을 처리하도록 가입자 호/연결 제어 소프트웨어를 구현하였다.

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A Congestion Control Method for Real-Time Communication Based on ATM Networks

  • Zhang, Lichen
    • Proceedings of the IEEK Conference
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    • 2002.07c
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    • pp.1831-1834
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    • 2002
  • In this paper, we present results of a study of congestion control for real-time communication based on ATM networks. In ATM networks, congestion usually results in cell loss. Based on the time limit and priority, the cells that compete for the same output line could be lined according to the character of real-time service. We adopt priority control algorithm for providing different QoS bearer services that can be implemented by using threshold methods at the ATM switching nodes, the cells of different deadline and priority could be deal with according to the necessity. Experiments show the proposed algorithm is effective in the congestion control of ATM real-time networks

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Human domain paradigm for man-machine interface system design in ATM switching system development (ATM 시스템 개발에서의 인간-기계 계면체계 설계를 위한 인간영역 정의)

  • Park, Beom;Kim, Bong-Su;Lee, Byung-Yoon;Kim, Han-Gyung
    • Proceedings of the ESK Conference
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    • 1993.10a
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    • pp.56-61
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    • 1993
  • 본 연구는 ATM 시스템 개발에 있어서 인간-기계 계면체계에 더 적합한 설계 계획을 위한 새로 운 인간영역에 관한 정의이다. ATM은 광대역 종합정보통신망에 사용될 비동기 전송방식 교환시 스템으로 인간-기계 시스템 상호작용에 있어서 인간 운용자에게 높은 신뢰성과 양호한 적응성이 강력히 요구된다. 대형 통신시스템의 설계영역 정의에 대한 이런 관점은 다음과 같은 관련 영역 을 포함하고 있다: 인간-기계 시스템의 구성요소: 객체지향적 설계 계획: 인간 프로세서 체계 모 형의 영역: 인지작용의 원칙: 인간오류 행위의 영역 등 이다. 또한, 제안하는 지식베이스 체계 는 인간-기계 계면기능의 평가에 있어서 인간지향적 오류의 진단분석을 유용하게 할 수 있다. 이 적합한 인간지향적 영역 정의는 ATM 통신 교환체계의 운용보전에 있어서 적합한 설계영역을 위한 주요한 지식기반이 될 것이며, 사용자에 편리한 운용체계의 개발로 효율적인 성과를 가져 올 것 이다.

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Perfomance Analysis for the IPC Interface Part in a Distributed ATM Switching Control System (분산 ATM 교환제어시스템에서 프로세서간 통신 정합부에 대한 성능 분석)

  • Yeo, Hwan-Geun;Song, Kwang-Suk;Ro, Soong-Hwan;Ki, Jang-Geun
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.6
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    • pp.25-35
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    • 1998
  • The control system architecture in switching systems have undergone numerous changes to provide various call processing capability needed in telecommunication services. During call processing in a distributed switching control environment, the delay effect due to communication among main processors or peripheral controllers is one of the limiting factors which affect the system performance. In this paper, we propose a performance model for an IPC(Inter Processor Communication) interface hardware block which is required on the ATM cell-based message processing in a distributed ATM exchange system, and analyze the primary causes which affect the processor performance through the simulation. Consequently, It can be shown that the local CPU of the several components(resources) related to the IPC scheme is a bottleneck factor in achieving the maximum system performance from the simulation results, such as the utilization of each processing component according to the change of the input message rate, and the queue length and processing delay according to input message rate. And we also give some useful results such as the maximum message processing capacity according to the change of the performance of local CPU, and the local CPU maximum throughput according to the change of average message length, which is applicable as a reference data for the improvement or expansion of the ATM control system.

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A Study on Design and Implementation of a VC-Merge Capable LSR on MPLS over ATM (ATM기반 MPLS망에서 확장성을 고려한 VC-Merge 가능한 LSR 설계에 관한 연구)

  • Kim, Young-Chul;Lee, Tae-Won;Lee, Dong-Won;Choi, Deok-Jae;Lee, Guee-Sang
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.12
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    • pp.29-38
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    • 2001
  • Recently, as Internet and its services grow rapidly, IETF(Internet Engineering Task Force) introduced a new switching mechanism, MPLS(Multi-Protocol Label Switching), to solve the problem of the scalability in Internet backbone. In this paper, we implemented the LSR loaded with VC-merging function, which causes LSR's management cost to be significantly reduced. We propose a new VC-merge function which supports differentiated services. In case of network congestion in the output buffer of each core LSR, appling link polices to the output modules of the LSR using the EPD algorithm can prevent the buffer from being overflowed. Simulation was performed for Diffserv by using multiple traffic models and investigated the impact of VC-merge method compared to non VC-merge method. The proposed switch is modeled in VHDL and fabricated using the SAMSUNG $0.5{\mu}m$ SOG process.

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