• The Transactions of the Korea Information Processing Society
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• v.6 no.1
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• pp.167-174
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• 1999

In this paper, we propose the adaptive separated-queueing ATM switching model for the effective processing of the various types of multimedia traffic by virtue of ATM switching network with multiple outlets which is the essential part of B-ISDN. This proposed model employs the dynamically separated buffering mechanism in the processing of two classes of cell, realtime service traffic and non-realtime service traffic, at the output buffer to enhance the overall QoS(Quality of Service). The adopted ATM switch architecture has Batcher-banyan based network, but it uses different topologies and control techniques 6to resolve the cell contention. For the performance evaluation of our proposed method, we have done both analytical modeling and simulation. The both results show that our proposed queueing strategy is quite appropriate to the ATM switch with multiple outlets and can quarantee the QoS requirements of the incoming multimedia traffic.

• Journal of Korea Society of Industrial Information Systems
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• v.10 no.1
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• pp.49-57
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• 2005

ATM Form has defined the guaranteed frame rate (GFR) service to provide minimum cell rate (MCR) guarantees for TCP traffic in ATM networks and allow it to fairly share residual bandwidth. GFR switch implementation consists of the frame-based generic cell rate algorithm (F-GCRA) and a frame forwarding mechanism. The F-GCRA identifies frames that are eligible for an MCR guarantee. The frame forwarding mechanism buffers cells at a frame unit according to information provided by the F-GCRA and forwards the buffered cells to an output port according to its scheduling discipline. A simple GFR mechanism with shared buffer with a global threshold is a feasible implementation mechanism, but has been known that it is insufficient to guarantee the MCR. This paper has estimated performance of GFR service for TCP traffic over ATM switches with the simple FIFO-based mechanism

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.8A
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• pp.569-580
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• 2003

One of the important advantages of multichannel switches is the incorporation of inherent fault tolerance into the switching fabric. For example, if a link which belongs to the multichannel group fails, the remaining links can assume responsibility for some of the traffic on the failed link. On the other hand, if faults occur in the switching elements, it can lead to erroneous routing and sequencing in the multichannel switch. We investigate several fault localization algorithms in multichannel crossbar ATM switches with a view to early fault recovery, The optimal algorithm gives the best performance in terms of time to localization but is computationally complex which makes it difficult to implement. We develop an on-line algorithm which is computationally mote efficient than the optimal algorithm. We evaluate its performance through simulation. The simulation results show that performance of the on line algorithm is only slightly sub-optimal for both random and bursty traffic. Finally a fault recovery algorithm is described which utilizes the information provided by the fault localization algorithm.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1999.12a
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• pp.103-111
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• 1999

ATM 망의 혼잡상태를 회피하기 위하여 다양한 방법들이 제안되고 있으며, 이들 중에는 전송시스템에 존재하는 스위치의 버퍼 값에 지능형 마킹을 표시함으로서 각 전송회선에 공평한 대역폭을 할당하며 혼잡상태를 회피하는 방법이 있다 ATM Forum은 ATM 망에서 ABR 서비스의 혼잡제어를 위한 표준으로서 셀률 기반 혼잡제어기법을 적용하고 있다. EPRCA(Enhanced Proprotional Rate Control Algorithm)은 망의 상태를 항상 검사하는 것이 아니라 망의 혼잡이 발생하였을 때만 작동하기 때문에 부정확한 셀률 정보를 가질 수 있다. DMRCA(Dynamic Max Rate Control Algorithm)은 혼잡의 정도에 따라서 적절한 셀률을 부여하기 위하여 스위치에 임계값을 지정하며, 셀률은 스위치에서 제공되는 증가계수와 감소계수에 비례하여 변하게 된다. 본 논문은 DMRCA에서 혼잡제어를 위해서 적용하는 증가/감소변수의 크기 변화에 따른 공평대역할당의 수렴속도를 평가하여 최적의 변수값을 찾고자 한다.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1992.04b
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• pp.457-465
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• 1992

현재 또는 장래에 예견되는 거의 모든 통신서비스를 통합적으로 제공할 수 있는 B-ISDN환경하에서 음성통화와 비디오정보, 데이타들이 각기 다른 bit rate와 서비스 요구조건(통화시간, 질등)를 가지고 전송서비스를 받으려 하기때문에 매우 다양한 서비스들의 조합을 고려하여 교환시스팀을 구현해야 한다. B-ISDN에 적합한 전송기술로서 ATM(Asynchronous Transfer Mode)이 일반적으로 제안되고 있는데 이미 10여종의 독특한 ATM시스팀들이 이론적, 실험적 연구단계를 거쳐 거의 실용화 단계까지 이르렀다고 주장되고 있다. 본 논문에서는 ATM교환시스팀의 설계요건과 비교기준을 제시하여 설계 대자인을 주어진 기술제약하에 최적화 할 수 있는 조건을 제시한다. 이때 우선 기본 스위치의 구조를 단단계로 할 것인가 다단계로 할 것인가에 대한 정량적, 확률적인 비교가 행해지고 특히 이미 많은 ATM스위치에서 채택되고 있는 Banyan형태의 망의 성능분석을 보다 현실에 근접하게 할 수 있는 이산적 마코프체인에 의한 모형과 계산방법이 확립된다. 이를 통해 단위스위치내부에 버퍼의 유무, 버퍼를 두는 위치, 또한 버퍼사이즈에 의한 영향등이 세부적으로 분석된다.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.115-123
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• 2002

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter. The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms. The Proposed switch acquires control over priority transmission through the REQ signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the Proposed switch under uniform traffic conditions.

• Journal of the Korea Society of Computer and Information
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• v.8 no.2
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• pp.97-105
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• 2003

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The Proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output Port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms . The proposed switch acquires control over priority transmission through the REd signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the proposed switch under non-uniform random traffic conditions.

• Journal of the Korea Society of Computer and Information
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• v.7 no.3
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• pp.80-91
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• 2002

A general goal of the AT%(Asynchronous Transfer Mode) network is to support connect across various network. On ATM networks, ABR services are provided using the remained ban after allocation CBR and VBR traffic. Realtime services such as transmitting audio or video data may be provided using CBR ado VBR which have a constrained transmission delay, but in these cases, the communications bandwidth may be wasted. In this paper a simulation has been performed to compare and evaluate the performance between the ERICA(Explicit Rate Indicate Avoidance) and EPRCA(Enhanced Proportional Rate Control Algorithm) switches which use Explicit Rate switch algorithm for ABR switch. The variation of the ACR at the source end system, the queue length, the utilization rate of the link bandwidth and the share fairness at the transient and steady states are used as the evaluation criteria for the simulation. As a result of simulation, ERICA algorithm switch was ten times long compared to ERPCA switch to achieve assigned fair share. so EPRCA switch is superior to ERICA about load response. For Fair share and stability, ERICA switch is excellent to EPRCA switch.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.4
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• pp.575-581
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• 1998

In order to accommodate current accelerated growth in customers and traffic. Internet has faced the demand to scale its network dimension both in size and bandwidth, and new service provisioning. One way to solve this problem is to forward If packets based on ATM switching technology. This paper briefly explained technical tasks to apply this If switching technique in ATM networks for building Internet backbone, and presented the directions to approach these tasks. Those tasks are scalability, ATM VC setup and mapping between VC and IP packet flow, traffic management and traffic engineering, multicast, and finally ATM switch architecture to provide multiservice.