• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.2
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• pp.41-47
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• 2008

Most of media compression CODECs adopts the variable length coding method. This paper proposes special registers and instruction set for bit stream process in order to accelerate the decoding process of the variable length code. The instruction set shares the conventional data path to minimize additional costs. And bit stream is read from the memory instead of the special port. Therefore the instruction set minimizes the change of the processor, and is adopted without any additional input controller and buffer, and accelerate decoding process of variable length code. The data path of the instruction set needs additional 65 bits memory and 344 equivalent gates, 0.19 ns delay under TSMC $0.25{\mu}m$ technology. The instruction set reduced the execution time of the variable length code decoding process in H.264/AVC by about 55%.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.159-166
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• 2013

This paper proposes an efficient loop accelerator for a motion estimation specific instruction-set processor. ME algorithms in nature contain complex and multiple loop operations. To support efficient hardware (HW) loop operations, this paper introduces four loop instructions and their specific HW architecture. The simulation results show that the proposed loop accelerator can reduce about 29% average instruction cycles for ME early-termination schemes compared with typical implementation having a combination of compare and conditional jump instructions. The proposed loop accelerator of the motion estimation specific instruction-set processor can significantly reduce the number of program memory accesses and greatly save power consumption. Hence, it can be quite suitable for low power and flexible ME implementation.

• The KIPS Transactions:PartA
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• v.19A no.1
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• pp.45-50
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• 2012

The demand for faster execution time and lower energy consumption has compelled architects of embedded processors to customize it to the needs of their target applications. These processors consequently provide a rich set of specialized instructions in order to enable programmers to access these features. Such an instruction is typically a $multi$-$output$ $instruction$ (MOI), which outputs multiple results parallely in order to exploit inherent underlying hardware parallelism. Earlier study has exhibited that MOIs help to enhance performance in aspect of instruction counts and code size. However the earlier algorithm does not consider the register pressure. So, some selected MOIs introduce register spill/reload code that increases the code size and instruction count. To attack this problem, we introduce a novel iterated instruction selection algorithm based on the register pressure of each selected MOIs. The experimental results show the suggested algorithm achieves 3% code-size reduction and 2.7% speed-up on average.

• Korean Journal of Poultry Science
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• v.41 no.1
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• pp.7-14
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• 2014

Tyrosinase (TYR) gene is located on chromosome 1 in chicken and it is composed of five exons and four introns. TYR gene is described as a key enzyme in melanin biosynthesis. Most examples of complete albinism in chicken have been due to defects in the tyrosinase gene. The association of feather color and sequence polymorphism in the Tyrosinase (TYR) gene was investigated using Korean Native chicken H breed (H_PL), Korean Native chicken L/W breed(L/W_PL) and 'Woorimatdag' commercial chickens (Woorimatdag_CC). From L_PL and W_PL breed analyses, 4 synonymous SNPs (locus G33A, G116A, C217T and C247T) and 2 SNPs (G838A and G958A) were detected in 4th exon and 4th intron of TYR gene respectively. The genotype frequencies for 6 SNPs were compared between L_PL and W_PL and W_PL represented homozygous SNP types in all the analyzed SNP positions while L_PL displayed various SNP types.