• International Journal of Aeronautical and Space Sciences
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• v.17 no.2
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• pp.232-239
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• 2016

Recently, in order to increase the efficiency and mission success rate of UAVs (Unmanned Aerial Vehicles), the necessity for formation flights is increased. In general, GPS (Global Positioning System) is used to obtain the relative position of leader with respect to follower in formation flight. However, it can't be utilized in environment where GPS jamming may occur or communication is impossible. Therefore, in this study, monocular vision is used for measuring relative position. General PC-based vision processing systems has larger size than embedded systems and is hard to install on small vehicles. Thus FPGA-based processing board is used to make our system small and compact. The processing system is divided into two blocks, PL(Programmable Logic) and PS(Processing system). PL is consisted of many parallel logic arrays and it can handle large amount of data fast, and it is designed in hardware-wise. PS is consisted of conventional processing unit like ARM processor in hardware-wise and sequential processing algorithm is installed on it. Consequentially HW/SW co-designed FPGA system is used for processing input images and measuring a relative 3D position of the leader, and this system showed RMSE accuracy of 0.42 cm ~ 0.51 cm.

• Proceedings of the Korea Contents Association Conference
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• 2005.11a
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• pp.264-268
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• 2005

This paper describes user context awareness system, which is one of the most essential technologies in various application services of ubiquitous computing. The proposed system used two-axial accelerometer, embedded in $SenseWear^{(R)}$ PRO2 Armband (BodyMedia). It was worn on the right upper arm of the experiment subjects. Using this data, PC-based fuzzy inference system was realized to distinguish human motion states, such as, tying, sitting, walking and running. The recognition rates of human motion states were 100 %, 98.64 %, 99.27 % and 100 % respectively for tying, sitting, walking and running.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.83-93
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• 2013

Recently, the SURF algorithm, which is conjugated for object tracking system as part of many computer vision applications, is a well-known scale- and rotation-invariant feature detection algorithm. The SURF, due to its high computational complexity, there is essential to develop a hardware accelerator in order to be used on an IP in embedded environment. However, the SURF requires a huge local memory, causing many problems that increase the chip size and decrease the value of IP in ASIC and SoC system design. In this paper, we proposed a way to design a SURF algorithm in hardware with greatly reduced local memory by partitioning the algorithms into several Sub-IPs using external memory and a DMA. To justify validity of the proposed method, we developed an example of simplified object tracking algorithm. The execution speed of the hardware IP was about 31 frame/sec, the logic size was about 74Kgate in the 30nm technology with 81Kbytes local memory in the embedded system platform consisting of ARM Cortex-M0 processor, AMBA bus(AHB-lite and APB), DMA and a SDRAM controller. Hence, it can be used to the hardware IP of SoC Chip. If the image processing algorithm akin to SURF is applied to the method proposed in this paper, it is expected that it can implement an efficient hardware design for target application.

• Journal of Korea Multimedia Society
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• v.15 no.10
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• pp.1247-1256
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• 2012

There are many filter based image processing algorithms and they usually require a huge amount of computations and memory accesses making it hard to attain a real-time performance, expecially in embedded applications. In this paper, we propose a pipelined hardware structure of the filter based face detection algorithm to show that the real time performance can be achieved by hardware design. In our design, the whole computation is divided into three pipeline stages: resizing the image (Resize), Transforming the image (ICT), and finding candidate area (Find Candidate). Each stage is optimized by considering the parallelism of the computation to reduce the number of cycles and utilizing the line memory to minimize the memory accesses. The resulting hardware uses 507 KB internal SRAM and occupies 9,039 LUTs when synthesized and configured on Xilinx Virtex5LX330 FPGA. It can operate at maximum 165MHz clock, giving the performance of 108 frame/sec, while detecting up to 20 faces.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.485-496
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• 2008

As the complexity of SoC (System-on-Chip) design increases dramatically. traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages. and hardware software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted ion levels only, which makes it difficult to integrate HW-SW cosimulators with different ion levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of ion levels and description languages, it allows us to generate simulation models with various ion levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully.

• Journal of Positioning, Navigation, and Timing
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• v.6 no.4
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• pp.167-179
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• 2017

In this paper, a simplified Cubature Kalman Filter (SCKF) is proposed to reduce the computation load of CKF, which is then used as a filter for transfer alignment of shipboard INS. CKF is an approximate Bayesian filter that can be applied to non-linear systems. When an initial estimation error is large, convergence characteristic of the CKF is more stable than that of the Extended Kalman Filter (EKF), and the reliability of the filter operation is more ensured than that of the Unscented Kalman Filter (UKF). However, when a system degree is large, the computation amount of CKF is also increased significantly, becoming a burden on real-time implementation in embedded systems. A simplified CKF is proposed to address this problem. This filter is applied to shipboard inertial navigation system (INS) transfer alignment. In the filter design for transfer alignment, measurement type and measurement update rate should be determined first, and if an application target is a ship, lever-arm problem, flexure of the hull, and asynchronous time problem between Master Inertial Navigation System (MINS) and Slave Inertial Navigation System (SINS) should be taken into consideration. In this paper, a transfer alignment filter based on SCKF is designed by considering these problems, and its performance is validated based on simulations.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.04a
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• pp.8-11
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• 2014

가상 데스크탑은 서버상에 서버 가상화 기술을 사용하여 다수의 가상 머신을 실행하고, 이를 네트워크로 연결된 클라이언트에서 사용하는 기술이다. 이러한, 가상 데스크탑이 대중화됨에 따라 다양한 형태의 클라이언트들이 시장에 존재한다. 본 논문에서는 ARM 임베디드 시스템 기반의 가상 데스크탑 클라이언트를 제안한다. 본 논문에서 제안하는 클라이언트는 임베디드 시스템 기반으로 소형화 및 저전력을 기본 특징으로 하며, 하드웨어, 운영체제, 가상 데스트탑 소프트웨어 모듈로 구성된다. 가상 데스크탑 소프트웨어 모듈은 사용자 인증을 통하여 가상 데스크탑 서버에 접속하고, 가상 데스크탑 뷰어를 통하여 서버의 가상 데스크탑을 사용한다. 본 클라이언트는 실제 가상 데스크탑 서버에 접속하여 동작 실험을 하였으며, 동영상 서비스까지 수행하는데 성능상에 문제가 없음을 확인하였다.

• The Journal of the Korea Contents Association
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• v.5 no.5
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• pp.287-295
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• 2005

This paper describes user context awareness system, which is one of the most essential technologies in various application services of ubiquitous computing. The proposed system used two-akial accelerometer, embedded in SenseWear(R)PRO2 Armband (BodyMedia). When it was worn on the right upper arm of the experiment subjects, MAD (mean of absolute difference) value of the sensor data was calculated to quantify the amount of the wear's activity. Using this data, PC-based fuzzy inference system was realized to distinguish human motion states, such as, lying, sitting, walking and running and to recognize the restricted emergency situations. In laboratory experiment, the amount of activities for tying, sitting, walking and running were 0.204 g/s, 0.373 g/s, 2.808 g/s and 16.243 g/s respectively. The recognition rates of human motion states were 96.7 %, 93.0 %, 95.2 % and 98.4 % respectively for lying, sitting, walking and running. The recognition rate of restricted emergency situation was 100%.

• Journal of IKEEE
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• v.21 no.4
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• pp.388-396
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• 2017

Since there are many variables such as various poses, illuminations and occlusions in a face detection problem, a high performance detection system is required. Although CNN is excellent in image classification, CNN operatioin requires high-performance hardware resources. But low cost low power environments are essential for small and mobile systems. So in this paper, the CPU-FPGA integrated system is designed based on 3-stage cascade CNN architecture using small size FPGA. Adaptive Region of Interest (ROI) is applied to reduce the number of CNN operations using face information of the previous frame. We use a Field Programmable Gate Array(FPGA) to accelerate the CNN computations. The accelerator reads multiple featuremap at once on the FPGA and performs a Multiply-Accumulate (MAC) operation in parallel for convolution operation. The system is implemented on Altera Cyclone V FPGA in which ARM Cortex A-9 and on-chip SRAM are embedded. The system runs at 30FPS with HD resolution input images. The CPU-FPGA integrated system showed 8.5 times of the power efficiency compared to systems using CPU only.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.5
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• pp.66-73
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• 2011

I try to solve the problem of the usage of the general software interrupt with the nested call of the software interrupt and the effective passing way of the parameters. The software interrupt should be protected against the indiscriminate access because it is used to call the system functions or to use the system resources by generating a software interrupt. But, it is difficult to effectively handle the SWI instruction because of its limited usage. I designed and implemented nested call of the software interrupt and the effective way that handle the parameters in the software interrupt service routine to solve this problem in this paper. In other words, from the single SWI call to the nested SWI call, I improved the software interrupt use all the more flexibly, and I compared and analyzed the strong and weak points of the two passing ways of the parameters. The main differences between these two ways are speed and readability. The stack pointer getting way incurred a lot of overhead although it has a very great readability. But, the stack pointer passing way producted 19% of the effectivity in speed by reduce overhead.