• Journal of KIISE:Computer Systems and Theory
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• v.32 no.9
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• pp.465-474
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• 2005

For high density SoC design, on-chip communication based on bus interconnection encounters bandwidth limitation while an NoC(Network-on-Chip) approach suffers from unacceptable complexity in its Implementation. This paper introduces a new on-chip communication protocol, SNP (SoC Network Protocol) to overcome these problems. In SNP, conventional on-chip bus signals are categorized into three groups, control, address, and data and only one set of wires is used to transmit all three groups of signals, resulting in the dramatic decrease of the number of wires. SNP efficiently supports master-master communication as well as master-slave communication with symmetric channels. A sequencing rule of signal groups is defined as a part of SNP specification and a phase-restoration feature is proposed to avoid redundant signals transmitted repeatedly over back-to-back transactions. Simulation results show that SNP provides about the same bandwidth with only $54\%$ of wires when compared with AMBA AHB.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.251-253
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• 2019

This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1733-1736
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• 2005

본 논문에서는 기존의 설계 방법의 문제점을 해결하기 위한 설계 방법인 플랫폼 기반 설계에서 사용할 수 있는 DSP 기반 플랫폼을 구현하였다. 구현된 DSP 기반 플랫폼을 AMBA AHB 버스를 바탕으로한 듀얼프로세서 플랫폼과 crossbar switch 구조의 버스 구조를 가지고 4개의 프로세서를 연결한 멀티프로세서 플랫폼으로 확장하여 검증함으로서 이질적인 환경에서 동작함을 나타내었다. 멀티프로세서 플랫폼에서는 DVB-T baseband 수신기를 HW/SW 분할 구현하고 성능 평가를 수행하였다. DSP 기반 플랫폼은 유연성, 확장성, 고속의 연산의 특징을 가진다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.712-713
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• 2011

In this paper, the AMBA AXI slave unit that can verify the pipelined arithmetic unit is proposed and the 2-stage 16-bit pipelined multiplier is introduced as design example. The proposed AXI slave unit consists of input buffer block memory, control registers, pipelined arithmetic unit, control unit, output buffer block memory, and AXI slave interface unit. The main operational procedures are divided into the following steps, such as burst-mode input data loading for the input buffer memory, programming of control registers, arithmetic operations for block data in the input buffer memory, and burst-mode output data unloading from output buffer memory to host processor. Because the proposed AXI slave unit is general structure, it can be efficiently applicable to AMBA AXI and AHB slave unit with pipelined arithmetic unit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.126-133
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• 2006

This paper describes an AMBA-based IP to perform forward and inverse transform and quantization required in the H.264 video compression standard. The transform and quantization circuit was optimized for area and performance. The AHB wrapper was added to the circuit for the AMBA-based operation. The user of the IP can specify how long the bus may be occupied by the IP and also where the video data are stored in the external memory. The function of the proposed IP based on AMBA Specification was verified on the platform board with Xilinx FPGA and ARM9 processor. We fabricated an MPW chip using $0.25{\mu}m$ standard cells and observed its correct operations on silicon.

• The Journal of the Korea Contents Association
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• v.6 no.11
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• pp.225-234
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• 2006

In this paper, we design a combined security processor, ECC, MD-5, and AES, as a SIP for cryptography of securing contents. Each SIP is modeled and designed in VHDL and implemented as a reusable macro through logic synthesis, simulation and FPGA verification. To communicate with an ARM9 core, we design a BFM(Bus Functional Model) according to AMBA AHB specification. The combined security SIP for a platform-based SoC is implemented by integrating ECC, AES and MD-5 using the design kit including the ARM9 RISC core, one million-gate FPGA. Finally, it is fabricated into a MPW chip using Magna chip $0.25{\mu}m(4.7mm{\times}4.7mm$) CMOS technology.

• Review of KIISC
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• v.16 no.3
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• pp.25-33
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• 2006

본 논문에서는 임베디드 시스템 온칩 적용을 위한 통합 보안 프로세서를 SIP(Semiconductor Intellectual Property)로 설계하였다. 각각의 SIP는 VHDL RTL로 모델링하였으며, 논리합성, 시뮬레이션, FPGA 검증을 통해 재사용이 가능하도록 구현하였다. 또한 ARM9과 SIP들이 서로 통신이 가능하도록 AMBA AHB의 스펙에 따라 버스동작모델을 설계, 검증하였다. 플랫폼기반의 통합 보안 SIP는 ECC, AES, MD-5가 내부 코어를 이루고 있으며 각각의 SIP들은 ARM9과 100만 게이트 FPGA가 내장된 디바이스를 사용하여 검증하였으며 최종적으로 매그나칩 $0.25{\mu}m(4.7mm\times4.7mm)$ CMOS 공정을 사용하여 MPW(Multi-Project Wafer) 칩으로 제작하였다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.961-962
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• 2006

The AMBA(Advanced Microcontroller Bus Architecture) system is one of the most important elements having an influence upon system performance in ARM-based SoC environments. The system guarantees easy connection and good performance as a 32-bit bus system for ARM processors. In this paper, we analyze arbitration algorithms for the AHB bus of the AMBA system and propose an efficient algorithm to improve the performance of the bus system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.137-146
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• 2005

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Interface modules for communication between system buses and IPs are required, since many IPs employ different protocols. Automatic generation of these interface modules would enhance designer's productivity and IP's reusability. This paper proposes an automatic interface generation system based on FSM generated from the protocol description of IPs. The proposed system provides the library modules for the standard buses to reduce the burdens of describing the protocols for data transfer from/to standard buses. Experimental results show that the area of the interface circuits generated by the proposed system had been increased slightly by 4.5% on the average when compared to manual designs. In the experiment, where bus clock is 100 Mhz and slave module clock is 34 Mhz, the latency of the interface had been increased by 7.1% in burst mode to transfer 16 data words. However, occupation of system bus can be reduce by 64.9%. A chip designer can generate an interface that improves the efficiency of system bus, by using this system.