• Transactions of Materials Processing
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• v.3 no.3
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• pp.359-374
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• 1994

Process sequence design in sheet metal forming process by the finite element method is investigated. The forming of sheet metal into a washing machine container is used to demonstrate the design of an improved process sequence which has fewer operations. The design procedure makes extensive use of the finite element method which has simulation capabilities of elastic-plastic modeling. A one-stage process to make an initial blank to the final product is simulated to obtain information on metal flow requirements. Loading simulation for a conventional method is also performed to evaluate the design criteria which are uniform thickness distribution around the finished part and maximum punch load within limit of available press capacity. The newly designed sequence has two forming operations and can achieve net-shape manufacturing, while the conventional process sequence has three forming operations. This specific case conventional process sequence has three forming operations. This specific case can be considered for application of the method and for development of the sequence design methodology in general.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.05a
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• pp.517-519
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• 2022

In 5G network environment, proactive mobility management is essential as 5G mobile networks provide new services with ultra-low latency through dense deployment of small cells. The importance of a system that actively controls device handover is emerging and it is essential to predict mobile trajectory during handover. Sequence-to-sequence model is a kind of deep learning model where it converts sequences from one domain to sequences in another domain, and mainly used in natural language processing. In this paper, we developed a system for predicting mobile trajectory in a wireless network environment using sequence-to-sequence model. Handover speed can be increased by utilize our sequence-to-sequence model in actual mobile network environment.

• Microbiology and Biotechnology Letters
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• v.25 no.1
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• pp.23-29
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• 1997

The nucleotide sequence of the estI gene encoding acetylxylan esterase I of Bacillus stearothermophilus was determined and analyzed. The estI gene was found to consist of a 810 base pair open reading frame coding for a polypeptide of 270 amino acids with a deduced molecular weight of 30 kDa. This was in well agreement with the molecular weight (29 kDa) estimated by SDS-PAGE of the purified esterase. The coding sequence was preceded by a putative ribo some binding site 10 bp upsteam of the ATG codon. Further 53 bp upstream, the transcription initiation signals were identified. The putative $_{-}$10 sequence (TCCAAT) and $_{-}$35 seqence (TTGAAT) corresponded closely to the respective consensus sequences for the Bacillus subtiis major RNA polymerase. The G+C content of the coding region of the estI was 51% whereas that of the third position of codone was 60.2%. The N-terminal amino acid sequence of the EstI deduced from the nucleotide sequence perfectly matched the corresponding region of the purified esterase described previously. Comparison with the amino acid sequence of other esterases and lipases reported so far allowed us to identify a sequence, GLSMG at positions 123 to 127 of the EstI which was reported to be the highly conserved active site sequence for those enzymes. The nucleotide sequence of the estI revealed 55.7% homology to that of the xylC coding for the acetylxylan esterase of Caldocellum saccharolyticum.

• The Mathematical Education
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• v.10 no.1
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• pp.4-5
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• 1972

이 논문은 modules 사이의 homomorphisms의 exact sequence에서 다음과 같은 것을 밝힌 것임. 1. (equation omitted)이 하나의 exact sequence 이고 P가 임의의 R-module일 때 (equation omitted)은 abelian group의 하나의 exact sequence라는 것. 2. (equation omitted)이 exact sequence 이고 P가 임의의 R-modele이면 (equation omitted)는 abelian group의 하나의 exact sequence라는 것.

• The Mathematical Education
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• v.14 no.1
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• pp.22-26
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• 1975

In this paper, we define a differential module and study its properties. In section 2, as for propositions, Ive research some properties, directsum, isomorphism of factorization, exact sequence of derived modules. And then as for theorem, I try to present the following statement, if the sequence of homomorphisms of differential modules is exact. Then the sequence of homomorphisms of Z(X) is exact, also the sequence of homomorphisms of Z(X) is exact. According to the theorem, as for Lemma, we consider commutative diagram between exact sequence of Z(X) and exact sequence of Z'(X) . As an immediate consequence of this theorem, we obtain the following result. If M is an arbitrary module and the sequence of homomorphisms of the modules Z(X) is exact, then the sequence of their tensor products with the trivial endomorphism is semi-exact.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.5
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• pp.55-61
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• 2010

When we design the control system used Programmable Logic Controller(PLC) by Sequential Function Chart(SFC), if we use a SFC, it is easy to know the sequential flow of control, to maintenance the controller and to describe a program. We program a SFC by a unique sequence, an alternative sequence and a parallel sequence. If we program a SFC by a alternative sequence, the memory size of a alternative sequence must be larger than the memory size of a unique sequence. Therefore this thesis show an efficient method to reduce a memory size and we confirmed its feasibility through actual example.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.99-104
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• 2000

In this paper, as a digital watermark we propose to use a chaotic sequence instead of the conventional Gaussian sequence. It is relatively easy to generate the chaotic sequence and is very sensitive to the change of initial value. The chaotic sequence adopted in this paper is a modified version of logistic map to give the sequence distribution of Chebyshev map. In the experiments, we applied the Gaussian sequence and chaotic sequence to wavelet coefficients of images to compare the similarity distribution. The results show that, as id the DCT-based watermarking system, the chaotic sequence is robust for various signal processing attacks, Moreover, the similarity variance is smaller than the Gaussian sequence for iterative experiments. It also shows a better performance for compression errors than the Gaussian sequence.

• Communications of the Korean Mathematical Society
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• v.11 no.1
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• pp.235-244
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• 1996

For a self-map f of a CW-pair (X, A), we introduce the G(f)-sequence of (X, A) which consists of subgroups of homotopy groups in the homotopy sequence of (X, A) and show some properties of the relative homotopy Jian groups. We also show a condition for the G(f)-sequence to be exact.

• Honam Mathematical Journal
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• v.41 no.4
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• pp.725-744
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• 2019

In this paper we introduce some new types of double difference sequence spaces defined by a new definition of convergence of double sequences and a double series with the help of sequence of Orlicz functions and a four dimensional bounded regular matrices A = (a_rtkl). We also make an effort to study some topological properties and inclusion relations between these sequence spaces. Finally, we compute the closed ideals in the space 𝑙²_∞.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.