• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.76-83
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• 2007

This paper describes a low power ROM using single charge-sharing capacitor and hierarchical bit line (SCSC-ROM). The SCSC-ROM reduces the power consumption in bit lines. It lowers the swing voltage of bit lines to a very small voltage by using a charge-sharing technique with a single capacitor. It implements the capacitor with dummy bit lines to improve noise immunity and make easy to design. The hierarchical bit line further saves the power by reducing the capacitance in bit lines. The SCSC-ROM also reduces the power consumption in control unit and predecoder by using the hierarchical word line decoder. The simulation result shows that the SCSC-ROM with $4K{\times}32bits$consumes only 37% power of a conventional ROM. A SCSC-ROM chip is fabricated in a $0.25{\mu}m$ CMOS process. It consumes 8.2mW at 240MHz with 2.5V.

• Journal of the Korea Society of Computer and Information
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• v.17 no.10
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• pp.11-23
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• 2012

To achieve efficient code size reduction, this paper proposes a new compressed instruction set architecture for the OpenRISC architecture. The new instructions and their corresponding formats are designed by the profiling information of the existing instruction usage. New 16-bit instructions and 32-bit instructions are proposed to compressed the existing 32-bit instructions and instruction sequences, respectively. The proposed instructions can be classified into three types. The first is the new 16-bit instructions for the frequent normal 32-bit instructions such as add, load, store, branch, and jump instructions. The second type is the new 32-bit instructions for the consecutive two load instructions, two store instructions, and 32-bit data mov instructions. Finally, two new 32-bit instructions are proposed to compress function prolog and epilog code, respectively. OpenRISC hardware decoder is extended to support the new instructions. Experiments show that the efficiency of code size reduction improves by an average of 30.4% when compared to the OR1200 instruction set architecture without loss of execution performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.64-69
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• 2013

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.

• The Korean Journal of Ceramics
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• v.4 no.2
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• pp.83-89
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• 1998

The structure refinements and the electrical and magnetoelectric measurements were performed for BIT.1BF and BIT.2BT. The tetragonal distortion of the ab plane became lessened with the addition of $4BiFeO_3 into Bi_4Ti_3O_{12}$ significantly. However, the tilting of the outer-oxygen octahedra of the perovskite unit and the elongatin of the $(Bi_2O_2)^{2+}$ layers became more pronounced. For the both phases, the bariations of dielectric properties and electrical conductivities at high temperatures showed that the ferroelectic I-rerroelectric II phase transition existed before reaching the Curie temperature. The electrical conductivity became higher with the increase of $Fe^{3+}$ ions, implying that the electron transfer increased correspondingly. The magnetoelectric effect was observed linear up to ~8 kOe, which was stronger in BIT.1BF than BIT.2BF. This behavior indicates that the distortion of the ab plane may affect the induced polarization as well as magnetic moment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.3
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• pp.153-163
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• 1986

GaAs, one of the III-V compounding semicondnctors, has been widely employed as base materials for the fabrication of the ultra-high-speed devices in the filelds of DBS, optical communications, MMIC'S and digital IC'S. There have been some reports on 4Kx4bit SRAM by D/E MESFET'S, 4K bit SRAM by HEMT'S, and receiver front ends for X-band by MMIC technologies, respectively. This paper reviews GaAs materials, wafer fabrication processes, device applications, and design aspects, and, finally, descusses the future of the ultra-high-spped-devices.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.12
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• pp.2479-2488
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• 1994

In this paper, a new dynamic excitation modeling scheme is proposed. Based upon the proposed excitation modeling scheme, two variable bit rate homomorphic vocoders are designed, whose average bit rates are 3.8 Kbps and 4.4 Kbps. The performance of the proposed excitation modeling scheme is then evaluated through the subjective listening tests. In the tests, the performances of two speech coders designed in this paper ate compared with the one of 4.8 Kbps homomorphic vocoder designed by Chung and Schafer, in which conventional static excitation modeling scheme applied. The subjective listening tests show that proposed dynamic excitation modeling scheme improves synthesized speech quality while lowering the average bit rate of speech coders.

• The Journal of Internal Korean Medicine
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• v.25 no.4
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• pp.274-288
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• 2004

Objectives : This study was designed to evaluate the effect on cytotoxicity of Bojungikki-tang(BIT) in human lung cancer H460 cells. Methods : BIT-induced cell death was confirmed as apoptosis characterized by chromatin condensation and increase of the $sub-G_1$, DNA content. It was tested whether the water extract of BIT affects the cell cycle regulators such as, p2l/Cipl, p27/Kipl, cyclin $B_1$. Results : The data showed that treatment of BIT decreased the viability of H460 cells in a dose-dependent manner. p2l/Cip1 is gradually decreased by the addition of the cells with BIT extract. Interestingly, p27/Kip1 is not detected for 24 hr after the addition of BIT extract, however, after 24 hr, p27/Kipl markedly increased. In addition, cyclin $B_1$, decreased in a time dependent manner after the addition of the water extract. The activation of caspase -3 protease was further confirmed by degradation of procaspase-8 protease andpoly(ADP-ribose) polymerase(P ARP) by BIT in H460 cells. Moreover, BIT induced the increase of Bak expression. Conclusion : These results suggest that the extract of BIT exerts anticancer effects to induce the death of human lung cancer H460 cells via down regulation of cell cycle regulators such as p2l/Cip1, and cyclin B1 or up regulation of cell cycle regulators such as p27/Kip1. Moerover results suggest that BIT induces an apoptosis in H460 cells via activation of intrinsic caspase cascades.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.11
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• pp.5381-5399
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• 2016

Currently, the quantize-and-forward (QF) scheme with high order modulation and quantization has rather high complexity and it is thus impractical, especially in multiple relay cooperative communications. To overcome these deficiencies, an improved low complex QF scheme is proposed by the combination of the low order binary phase shift keying (BPSK) modulation and the 1-bit and 2-bit quantization, respectively. In this scheme, the relay selection is optimized by the best relay position for best bit-error-rate (BER) performance, where the relays are located closely to the destination node. In addition, an optimal power allocation is also suggested on a total power constraint. Finally, the BER and the achievable rate of the low order 1-bit, 2-bit and 3-bit QF schemes are simulated and analyzed. Simulation results indicate that the 3-bit QF scheme has about 1.8~5 dB, 4.5~7.5 dB and 1~2.5 dB performance gains than those of the decode-and-forward (DF), the 1-bit and 2-bit QF schemes, at BER of $10^{-2}$, respectively. For the 2-bit QF, the scheme of the normalized Source-Relay (S-R) distance with 0.9 has about 5dB, 7.5dB, 9dB and 15dB gains than those of the distance with 0.7, 0.5, 0.3 and 0.1, respectively, at BER of $10^{-3}$. In addition, the proposed optimal power allocation saves about 2.5dB much more relay power on an average than that of the fixed power allocation. Therefore, the proposed QF scheme can obtain excellent features, such as good BER performance, low complexity and high power efficiency, which make it much pragmatic in the future cooperative communications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.35-42
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• 2010

This paper describes a 10 bit 80MHz CMOS D/A converter for wireless communication system. The proposed circuit in the paper is implemented with a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process. The architecture of the circuit consists of the 4bit LSB with binary decoder, and both the 3bit ULSB and the 3bit MSB with the thermometer decoder. The measurement results demonstrates SFDR of 60.42dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB of 8.75bit. INL and DNL have been measured to be ${\pm}$0.38LSB and ${\pm}$0.32LSB and glitch energy is measured to be 4.6$pV{\cdot}s$. Total power dissipation is 48mW at 80MHz(maximum sampling frequency) with a single power supply of 1.8V.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.3-10
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• 2017

Counting Bloom filters (CBFs) have been popularly used in many network algorithms and applications for the membership queries of dynamic sets, since CBFs can provide delete operations, which are not provided in a standard 1-bit vector Bloom filter. However, because of the counting functions, a CBF can have overflows and accordingly false negatives. CBFs composed of 4-bit counters are generally used, but the 4-bit CBF wastes memory spaces by allocating 4 bits for every counter. In this paper, we propose a simple alternative of a 4-bit CBF named ternary Bloom filter (TBF). In the proposed TBF structure, if two or more elements are mapped to a counter in programming, the counters are not used for insertion or deletion operations any more. When the TBF consumes the same amount of memory space as a 4-bit CBF, it is shown through simulation that the TBF provides a better false positive rate than the CBF as well as the TBF does not generate false negatives.