• Title/Summary/Keyword: 4-bit

Search Result 2,673, Processing Time 0.027 seconds

Wear assessment of the WC/Co cemented carbidetricone drillbits in an open pit mine

  • Saeidi, Omid;Elyasi, Ayub;Torabi, Seyed Rahman
    • Geomechanics and Engineering
    • /
    • v.8 no.4
    • /
    • pp.477-493
    • /
    • 2015
  • In rock drilling, the most important characteristic to clarify is the wear of the drill bits. The reason that the rock drill bits fail with time is wear. In dry sliding contact adhesive wear deteriorates the materials in contact, quickly, and is the result of shear fracture in the momentary contact joins between the surfaces. This paper aims at presenting an overview of the assessment of WC/Co cemented carbide (CC) tricone bit in rotary drilling. To study wear of these bits, two approaches have been used in this research. Firstly, the new bits were weighted before they mounted on the drill rigs and also after completion their useful life to obtain bit weight loss percentage. The characteristics of the rock types drilled by using such this bit were measured, simultaneously. Alternatively, to measure contact wear, namely, matrix wear a micrometer has been used with a resolution of 0.02 mm at different direction on the tricone bits. Equivalent quartz content (EQC), net quartz content (QC), muscovite content (Mu), coarseness index (CI) of drill cuttings and compressive strength of rocks (UCS) were obtained along with thin sections to investigate mineralogical properties in detail. The correlation between effective parameters and bit wear were obtained as result of this study. It was observed that UCS shows no significant correlation with bit wear. By increasing CI and cutting size of rocks wear of bit increases.

A Threshold Estimation Algorithm for a Noncoherent IR-UWB Receiver Using 1-bit Sampler (1-bit 샘플러를 사용한 비동기식 IR-UWB 수신기의 임계값 추정 알고리즘)

  • Lee, Soon-Woo;Park, Young-Jin;Kim, Kwan-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.44 no.8
    • /
    • pp.17-22
    • /
    • 2007
  • In this paper, we propose a threshold estimation algorithm for a noncoherent IR-UWB receiver using 1-bit sampler. The proposed method reduces the hardware complexity by using the information of binary data resulted from 1-bit sampler instead of measuring the energy level of a received signal. Besides, mathematical modeling shows that the performances are similar to those of theoretically optimal threshold in terms of bit error rate. Computer simulations based on the IEEE 802.15.4a channel model also demonstrate the superiority of the proposed algorithm.

A Study on the Performance Analysis of 4-ary Scaling Wavelet Shift Keying (4-ary 스케일링 웨이브릿 편이 변조 시스템의 성능 분석에 관한 연구)

  • Jeong, Tae-Il;Ryu, Tae-Kyung;Kim, Jong-Nam;Moon, Kwang-Seok;Kim, Hyun-Deok
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.14 no.5
    • /
    • pp.1155-1163
    • /
    • 2010
  • An algorithm of the conventional wavelet shift keying is carried out that the scaling function and wavelet are encoded to 1(mark) and 0(space) for the input binary data, respectively. Two bit modulation technique which uses four carrier frequencies is existed. Four carrier frequencies are defined as scaling function, inversed scaling function, wavelet, and inversed wavelet, which are encoded to 10, 11, 00 and 01, respectively. In this paper, we defined 4-ary SWSK (4-ary scaling wavelet shift keying) which is two bit modulation, and it is derived to the probability of bit error and symbol error of the defined system from QPSK. In order to analyze to the performance of 4-ary SWSK, we are obtained in terms of the probability of bit error and symbol error for QPSK (quadrature phase shift keying), MFSK(M-ary frequency shift keying) and proposed method. As a results of simulation, we confirmed that the proposed method was superior to the performance in terms of the probability of bit error and symbol error.

An Efficient Hardware Implementation of Square Root Computation over GF(p) (GF(p) 상의 제곱근 연산의 효율적인 하드웨어 구현)

  • Choe, Jun-Yeong;Shin, Kyung-Wook
    • Journal of IKEEE
    • /
    • v.23 no.4
    • /
    • pp.1321-1327
    • /
    • 2019
  • This paper describes an efficient hardware implementation of modular square root (MSQR) computation over GF(p), which is the operation needed to map plaintext messages to points on elliptic curves for elliptic curve (EC)-ElGamal public-key encryption. Our method supports five sizes of elliptic curves over GF(p) defined by the National Institute of Standards and Technology (NIST) standard. For the Koblitz curves and the pseudorandom curves with 192-bit, 256-bit, 384-bit and 521-bit, the Euler's Criterion based on the characteristic of the modulo values was applied. For the elliptic curves with 224-bit, the Tonelli-Shanks algorithm was simplified and applied to compute MSQR. The proposed method was implemented using the finite field arithmetic circuit with 32-bit datapath and memory block of elliptic curve cryptography (ECC) processor, and its hardware operation was verified by implementing it on the Virtex-5 field programmable gate array (FPGA) device. When the implemented circuit operates with a 50 MHz clock, the computation of MSQR takes about 18 ms for 224-bit pseudorandom curves and about 4 ms for 256-bit Koblitz curves.

Study on Image Distortions and Bit-rate Changes Induced by Watermark based-on $4{\times}4$ DCT of H.264/AVC (H.264/AVC의 $4{\times}4$ DCT기반 워터마크에 따른 영상왜곡과 비트율 변화에 대한 연구)

  • Kim, Sung-Min;Won, Chee-Sun
    • Journal of the Institute of Electronics Engineers of Korea SP
    • /
    • v.42 no.5 s.305
    • /
    • pp.115-122
    • /
    • 2005
  • There are some problems in directly applying the conventional MPEG bit-stream based watermarking schemes to the bit-stream of a new compression standard, H.264/AVC. In this paper we analyze the effects of the conventional DCT-based watermarking scheme to H.264/AVC, especially in terms of image distortions and bit-rate changes. It turns out that the intra-frame prediction md CAVLC of H.264/AVC with the watermarking worsen the image distortions and bit-rate changes. The experiment results show on average 28.17dB decrease in PSNR and 56.71% increase in bit-rate over all QPs.

A design of Software 2D BitBLT Engine based on RTOS (RTOS 기반의 소프트웨어 2D BitBLT 엔진의 설계)

  • Kim, Bong-Joo;Hong, Jiman
    • Journal of the Korea Society of Computer and Information
    • /
    • v.19 no.4
    • /
    • pp.35-41
    • /
    • 2014
  • In this paper, we proposed the implementation of software-based 2D BitBLT engine on the pSOS operating system and the operation of the BitBLT engine on patient monitoring device was verified. To verify the proposed method on the patient monitoring device, we designed prototype PCB board, and verified the operation. We designed the motherboard by using ARM9-based CPU. Because hardware-based BitBLT module was replaced with software-based one, CPU load problem was weighted. To solve this problem, w changed 400Mhz processor instead of 200Mhz processor. We implemented 2D BitBLT kernel module as a device driver which is one of the key elements of a graphics controller GUI in patient monitoring device.

Design of a Wireless Self-Powered Temperature Sensor for UHF Sensor Tags (무선 전력 구동 센서 태그 내장형 온도센서의 설계)

  • Kim, Hyun-Sik;Cho, Jung-Hyun;Kim, Shi-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.44 no.10
    • /
    • pp.1-6
    • /
    • 2007
  • Wireless Self-Powered Temperature Sensor for UHF Sensor Tags which are basic device for construction of ubiquitous sensor network is proposed. The key parameters of the target specification are resolution of $0.1\;^{\circ}C$ per output bit, below 1.5 V of operating voltage and below 5 uW of power consumption during sensing operation. Temperature sensor circuit consists of PTAT current generator, band gap reference circuit generating both reference voltage and current, Sigma-Delta Converter, and Digital Counter. Simulated maximum resolution was $0.23\;^{\circ}C/bit$ in 11-bit output. The proposed temperature sensor was fabricated by using a 0.25 m CMOS process. The chip area is $0.32\;{\times}\;0.22\;mm$ and the operating frequency is 2 MHz. Measured resolution from fabricated temperature sensor was $4\;^{\circ}C/bit$ in 8-bit output for the temperature range from $10^{\circ}C$ to $80^{\circ}C$.

Design of a Microwave PIN Diode 4-bit Phase Shifter (초고주파 PIN 다이오드 4-bit 변위기의 구현)

  • 노태문;김찬홍;전중창;박위상;김범만
    • Journal of the Korean Institute of Telematics and Electronics A
    • /
    • v.31A no.6
    • /
    • pp.45-52
    • /
    • 1994
  • A microwave PIN diode 4-bit phase shifter is designed in X-band. A loaded-line type is used for the 22.5$^{\circ}$ and 45$^{\circ}$ bits, and a switched-line type for the 90$^{\circ}$and 180$^{\circ}$bits. The measured results show that the phase error and average insertion loss are less than $\pm$5.4$^{\circ}$and 7.2dB, respectively, over a 9.75~10.25GHz frequency band.

  • PDF

Digital Variable Focal Liquid Lens (초점 조절이 가능한 디지털 유체 렌즈)

  • Lee, Dong-Woo;Cho, Young-Ho
    • Transactions of the Korean Society of Mechanical Engineers A
    • /
    • v.34 no.5
    • /
    • pp.557-560
    • /
    • 2010
  • We have designed a digital variable-focal-length liquid lens by using 4-bit actuators. Each bit actuator consists of 1, 2, 4, and 8 unit actuators, squeezes discrete fluidic volume of $2^4$ different levels into the lens The 4-bit digital actuation mode ($b_4b_3b_2b_1$) affords $2_4$ different lens curvatures and focal lengths. The on/off control of the bit actuators helps in solving the main problem associated with analog liquid lenses, i.e., precise control of the pressure or volume of the fluid for changing the lens curvature and focal length. Experimentally, it has been found that the 4-bit actuators allow 0.074 nl (${\pm}0.02\;nl$) of the given fluid per bit to enter the lens and help in increasing the focal length from 3.63 mm to 38.6 mm in $2^4$ different levels; no high-cost controllers are required for precise control of the pressure or volume in this case. Therefore, the present digital liquid lens is more suitable to integrated optical systems by reducing additional component for pressure and volume control.

Efficient Implementation of Single Error Correction and Double Error Detection Code with Check Bit Pre-computation for Memories

  • Cha, Sanguhn;Yoon, Hongil
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.12 no.4
    • /
    • pp.418-425
    • /
    • 2012
  • In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.