• Title/Summary/Keyword: 4-bit

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The DWA Design with Improved Structure by Clock Timing Control (클록 타이밍 조정에 의한 개선된 구조를 가지는 DWA 설계)

  • Kim, Dong-Gyun;Shin, Hong-Gyu;Cho, Seong-Ik
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.59 no.4
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    • pp.401-404
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    • 2010
  • In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.

An Implementation of a 4-Bit Diode Phase Shifter in the Parallel Plate Waveguide for the RADANT Lens (RADANT 렌즈를 위한 평행판 도파관 내에서의 4-비트 다이오드 위상변위기 구현)

  • Lee, Kee-Oh;Park, Dong-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.20 no.9
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    • pp.906-913
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    • 2009
  • In this paper, the design concept and implementation method of the X-band 4-bit($22.5^{\circ}$, $45^{\circ}$, $90^{\circ}$, $180^{\circ}$ BIT) diode phase shifter in the parallel plate waveguide are introduced. The simulated results of $11.25^{\circ}$, $22.5^{\circ}$ and $45^{\circ}$ dielectric phase shift layers using CST's MWS and Agilent's ADS are presented, and the measured results are compared with the simulated ones. The simulated phase shift errors at the center frequency are $0.6^{\circ}$, $0.7^{\circ}$, and $3.5^{\circ}$, respectively and the measured phase shift errors at the center frequency are $0.6^{\circ}$, $2^{\circ}$, and $5.5^{\circ}$, respectively. Also, the MWS simulated results of $22.5^{\circ}$ BIT and $45^{\circ}$ BIT phase shifter are presented and compared with the ADS simulated ones to verify the validity of the presented design concept and implementation method.

A Study on High Precision and High Stability Digital Magnet Power Supply Using Second Order Delta-Sigma modulation (2차 델타 시그마 변조기법을 이용한 고 정밀 및 고 안정 디지털 전자석 전원 장치에 관한 연구)

  • Kim, Kum-Su;Jang, Kil-Jin;Kim, Dong-Hee
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.29 no.3
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    • pp.69-80
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    • 2015
  • This paper is writing about developing magnet power supply. It is very important for power supply to obtain output current in high precision and high stability. As a switching noise and a power noise are the cause of disrupting the stability of output current, to remove these at the front end, low pass filter with 300Hz cutoff frequency is designed and placed. And also to minimize switching noise of the current into magnet and to stop abrupt fluctuations, output filter should be designed, when doing this, we design it by considering load has high value inductance. As power supply demands the stability of less than 5ppm, high precision 24bit(300nV/bit) analog digital converter is needed. As resolving power of 24bit(300nV/bit) analog digital converter is high, it is also very important to design the input stage of analog digital converter. To remove input noise, 4th order low pass filter is composed. Due to the limitation of clock, to minimize quantization error between 15bit DPWM and output of ADC having 24bit resolving power, ${\Sigma}-{\Delta}$ modulation is used and bit contracted DPWM is constituted. And before implementing, to maximize efficiency, simulink is used.

A Low Density Parity Check Coding using the Weighted Bit-flipping Method (가중치가 부과된 Bit-flipping 기법을 이용한 LDPC 코딩)

  • Joh, Kyung-Hyun;Ra, Keuk-Hwan
    • 전자공학회논문지 IE
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    • v.43 no.4
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    • pp.115-121
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    • 2006
  • In this paper, we proposed about data error check and correction on channel transmission in the communication system. LDPC codes are used for minimizing channel errors by modeling AWGN Channel as a VDSL system. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten. Also the performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. This algorithm is better than conventional algorithms to correct errors, the proposed algorithm assigns weights for errors concerning parity bits. The proposed weighted Bit-flipping algorithm is better than the conventional Bit-flipping algorithm and we are recognized improve gain rate of 1 dB.

Design of a High Performance 32$\times$32-bit Multiplier Based on Novel Compound Mode Logic and Sign Select Booth Encoder (새로운 복합모드로직과 사인선택 Booth 인코더를 이용한 고성능 32$\times$32-bit 곱셈기의 설계)

  • Kim, Jin-Hwa;Song, Min-Gyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.3
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    • pp.205-210
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    • 2001
  • In this paper, a novel compound mode logic based on the advantage of both CMOS logic and pass-transistor logic(PTL) is proposed. From the experimental results, the power-delay products of the compound mode logic is about 22% lower than that of the conventional CMOS logic, when we design a full adder. With the proposed logic, a high performance 32$\times$32-bit multiplier has been fabricated with 0.6um CMOS technology. It is composed of an improved sign select Booth encoder, an efficient data compressor based on the compound mode logic, and a 64-bit conditional sum adder with separated carry generation block. The Proposed 32$\times$32-bit multiplier is composed of 28,732 transistors with an active area of 1.59$\times$1.68 mm2 except for the testing circuits. From the measured results, the multiplication time of the 32$\times$32-bit multiplier is 9.8㎱ at a 3.3V power supply, and it consumes about 186㎽ at 100MHz.

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Preparation of a Bi$_{4}$Ti$_{3}$O$_{12}$ Thin Film and Its Electrical Properties (Bi$_{4}$Ti$_{3}$O$_{12}$ 박막의 제작과 그 특성에 관한 연구)

  • Gang, Seong-Jun;Jang, Dong-Hun;Min, Gyeong-Jin;Kim, Seong-Jin;Jeong, Yang-Hui;Yun, Yeong-Seop
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.4
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    • pp.7-14
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    • 2000
  • A Bi$_{4}$Ti$_{3}$O$_{12}$ (BIT) thin film is prepared by sol-gel method using acetate precursors and evaluated whether it could be applied to NVFRAM (Non-Volatile Ferroelectric RAM). The drying and the annealing temperature are 40$0^{\circ}C$ and $650^{\circ}C$, respectively and they are determined from the DT-TG (Differential Thermal-Thermal Gravimetric) analysis. The BIT thin film deposited on Pt/Ta/SiO$_{2}$/Si substrate shows orthorhombic perovskite phase. The grain size and the surface roughness are about 100 nm and 70.2$\AA$, respectively. The dielectric constant and the loss tangent at 10 KHz are 176 and 0.038, respectively, and the leakage current density at 100 ㎸/cm is 4.71 $mutextrm{A}$/$\textrm{cm}^2$. In the results of hysteresis loops measured at $\pm$250 ㎸/cm, the remanent polarization (Pt) and the coercive field (Ec) are 5.92 $\mu$C/$\textrm{cm}^2$ and 86.3 ㎸/cm, respectively. After applying 10$^{9}$ square pulses of $\pm$5V, the remanent polarization of the BIT thin film decreases as much as about 33% from 5.92 $\mu$C/$\textrm{cm}^2$ of initial state to 3.95 $\mu$C/$\textrm{cm}^2$.

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Fair Bit Allocation in Spatially Correlated Sensor Fields Using Shapley Value (공간 상관성을 갖는 센서장에서 섀플리 값을 이용한 공정한 비트 할당)

  • Sang-Seon Byun
    • IEMEK Journal of Embedded Systems and Applications
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    • v.18 no.4
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    • pp.195-201
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    • 2023
  • The degree of contribution each sensor makes towards the total information gathered by all sensors is not uniform in spatially correlated sensor fields. Considering bit allocation problem in such a spatially correlated sensor field, the number of bits to be allocated to each sensor should be proportional to the degree of contribution the sensor makes. In this paper, we deploy Shapley value, a representative solution concept in cooperative game theory, and utilize it in order to quantify the degree of contribution each sensor makes. Shapley value is a system that determines the contribution of an individual player when two or more players work in collaboration with each other. To this end, we cast the bit allocation problem into a cooperative game called bit allocation game where sensors are regarded as the players, and a payoff function is given in the criteria of mutual information. We show that the Shapley value fairly quantifies an individual sensor's contribution to the total payoff achieved by all sensors following its desirable properties. By numerical experiments, we confirm that sensor that needs more bits to cover its area has larger Shapley value in spatially correlated sensor fields.

A Novel Frequency-octupling Millimeter Wave ROF Without Bit Walk-off Effect Based on MZM and an Insertion Pilot Signal

  • Bin Li;Xu Chen;Siyuan Dai;Xinqiao Chen
    • Current Optics and Photonics
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    • v.8 no.4
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    • pp.345-354
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    • 2024
  • The bit walk-off effect caused by fiber dispersion and carrier reuse in the base station (BS) are two key problems in radio-over-fiber (ROF) systems. In this paper, a novel frequency-octupling ROF system based on the Mach-Zehnder modulator (MZM) is proposed, which can overcome the bit walk-off effect and realize carrier reuse by inserting pilot signals. Theoretical analysis and simulation verification of the system are carried out. Under the condition of a Q factor greater than 6, the optical fiber transmission distance of the upper and lower links is more than 290 km and 80 km, respectively. The influence of the main device parameters of the system on the Q factor is analyzed when they deviate from their designed values. The system designed in this paper can not only effectively overcome the bit walk-off effect, but also solve the problem of downlink performance degradation and the limitation of tunability caused by conventional carrier reuse in ROF. The system can greatly increase the transmission distance and improve the performance of the system and has an important application prospect in ROF.

Efficient Operator Design Using Variable Groups (변수그룹을 이용한 효율적인 연산기 설계)

  • Kim, Yong-Eun;Chung, Jin-Gyun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.1
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    • pp.37-42
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    • 2008
  • In this paper, we propose a partial product addition method using variable groups in the design of operators such as multipliers and digital filters. By this method, full adders can be replaced with simple logic circuits. To show the efficiency of the proposed method, we applied the method to the design of squarers and precomputer blocks of FIR filters. In case of 7 bit and 8 bit squarers, it is shown that by the proposed method, area, power and delay time can be reduced up to {22.1%, 20.1%, 14%} and {24.7%, 24.4%, 6.7%}, respectively, compared with the conventional method. The proposed FIR precomputer circuit leads to up to {63.6%, 34.4%, 9.8%} reduction in area, power consumption and propagation delay compared with previous method.

Error Correction Coding on the Transform Coded Image Transmission over Noisy Channel (잡음 채널에서 변환 부호화 영상 전송에 대한 에러 정정 부호)

  • 채종길;주언경
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.31B no.4
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    • pp.97-105
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    • 1994
  • Transform image coding using DCT is proved to be efficient in the absence of channel error but its performance degrades rapidly over noisy channel. In this paper, in the case of appling bit selcetive error correction coding that protects some significant bits in a codeword, an efficient allocation method of imformation bits and additive redundancy bits used for quantization and error correction coding respectively under constant transmission bit rate is proposed, and its performance is analyzed. As a result, without increasing trasmission bit rate, PSNR can be improved up to 7~8 [dB] below bit error rate $10^2$ and the image without blocking effect caused by bit error resulted from channel noise can be recostructed.

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