• Vacuum Magazine
• /
• v.3 no.2
• /
• pp.11-16
• /
• 2016

Tidal current energy is the most interesting renewable resources that have been less harnessed. Korea has globally outstanding tidal current energy resources and it is highly needed to develop a tidal current energy conversion system. It is reported that the total amount of available tidal current energy is approximately 6GW in Korea. A good tidal site candidate is required a large amount of fast moving water, bathymetry and seabed properties, no conflicts with other users and is close to a load and grid interconnection. In this review, we summarized the results of R&D projects regarding tidal current resources, utilization projects and demonstration test bed.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.29A no.7
• /
• pp.64-72
• /
• 1992

The capacitance for three-dimensional (3D) VLSI interconnection line is calculated. Capacitance is obtained by solving integral equation that is the product of Green's function and surface charge density. Surface charge density is assumed that constant in each subarea, and subarea is devided by rectangular size in interconnetion surfaces. Up to date, so this integral method using Green's function is calculated by Fourier integral transformation, that it cannot help making an error. In this paper, it is proposed to use direct integration instead of Fourier integral method. And we proved accuracy of this paper in comparision with conventional results.

• Journal of the Korea Society of Computer and Information
• /
• v.16 no.6
• /
• pp.1-10
• /
• 2011

In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently. Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.

• Journal of KIISE:Computer Systems and Theory
• /
• v.35 no.9_10
• /
• pp.421-428
• /
• 2008

A. Ghafoor proposed Even networks as a class of fault-tolerant multiprocessor networks in [1] and analyzed so many useful properties include node disjoint paths. By introducing node disjoint paths in [1], fault diameter of Even networks is d+2(d=odd) and d+3(d=even). But the lengths of node disjoint paths proved in [1] are not the shortest. In this paper, we show that Even network Ed is node symmetric. We also propose the shortest lengths of node disjoint paths using cyclic permutation, and fault diameter of Even networks is d+1.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.3
• /
• pp.189-195
• /
• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.06a
• /
• pp.183-184
• /
• 2007

A 40 Gb/s transimpedance amplifier IC was designed and fabricated with a InP/InGaAs HBTs technology. In this study, we interconnect 40Gbps trans impedance amplifier IC to a duroid substrate by a flip chip bonding instead of conventional wire bonding for interconnection. For flip chip bonding, we developed fine pitch bump with the $70{\mu}m$ diameter and $150{\mu}m$ pitch using WLP process. To study the effect of WLP, electrical performance was measured and analyzed in wafer and package module using WLP. The Small signal gains in wafer and package module were 7.24 dB and 6.93dB respectively. The difference of small signal gain in wafer and package module was 0.3dB. This small difference of gain is due to the short interconnection length by bump. The characteristics of return loss was under -10dB in both wafer and module. So, WLP process can be used for millimeter wave GaAs MMIC with the fine pitch pad and duroid substrate can be used in flip chip bonding process.

• Journal of Broadcast Engineering
• /
• v.27 no.2
• /
• pp.207-215
• /
• 2022

The latest volumetric technology's high geometrical accuracy and realism ensure a high degree of correspondence between the real object and the captured 3D model. Nevertheless, since the 3D model obtained in this way constitutes a sequence as a completely independent 3D model between frames, the consistency of the model surface structure (geometry) is not guaranteed for every frame, and the density of vertices is very high. It can be seen that the interconnection node (Edge) becomes very complicated. 3D models created using this technology are inherently different from models created in movie or video game production pipelines and are not suitable for direct use in applications such as real-time rendering, animation and simulation, and compression. In contrast, our method achieves consistency in the quality of the volumetric 3D model sequence by linking re-meshing, which ensures high consistency of the 3D model surface structure between frames and the gradual deformation and texture transfer through correspondence and matching of non-rigid surfaces. And It maintains the consistency of volumetric 3D model sequence quality and provides post-processing automation.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.5
• /
• pp.649-657
• /
• 2014

In this study, the effects of the frequency-dependent characteristics of through-silicon vias (TSVs) on the performance of 3D ICs are examined by evaluating a typical interconnection structure, which is composed of 32-nm CMOS inverter drivers and receivers connected through TSVs. The frequency-domain model of TSVs is extracted in S-parameter from a 3D electromagnetic (EM) method, where the dimensional variation effect of TSVs can be accurately considered for a comprehensive parameter sweep simulation. A parametric analysis shows that the propagation delay increases with the diameter and height of the TSVs but decreases with the pitch and liner thickness. We also investigate the crosstalk effect between TSVs by testing different signaling conditions. From the simulations, the worst signal integrity is observed when the signal experiences a simultaneously coupled transition in the opposite direction from the aggressor lines. Simulation results for nine-TSV bundles having regular and staggered patterns reveal that the proposed method can characterize TSV-based 3D interconnections of any dimensions and patterns.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.471-474
• /
• 1998

In this paper, we consider the problem of optimal broadcasting in recursive circulants under multi-port communication model. Recursive circulant G(N, d) that is defined to be a circulant graph with N vertices and jumps of powers of d is a useful interconnection network from the viewpoint of network metrices. Our model assumes that a processor can transmit a message to $\alpha$ neighboring processors simultaneously where $\alpha$ is two or three. For the broadcasting problem, we introduce 3-trees and 4-trees. And then we show that 3-trees and 4-trees are minimum broadcast trees in 2-port model and 3-port model. Using the above results, we show that recursive circulants g(2m, 2) have optimum broadcasting time in 2-port model and 3-port model.

• Proceedings of the KWS Conference
• /
• 2007.11a
• /
• pp.229-231
• /
• 2007

Recently, 3D-electronic packaging by TSV is in interest. TSV(Through Silicon Via) is a interconnection hole on Si-wafer filled with conducting metal such as Copper. In this research, chips with TSV are connected by electroplated Sn bump without PR. Then chips with TSV are put together and stacked by the methode of Reflow soldering. The stacking was successfully done and had no noticeable defects. By eliminating PR process, entire process can be reduced and makes it easier to apply on commercial production.