• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.1-6
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• 2014

The demand for fine-pitch devices is increasing due to an increase in I/O pin count, a reduction in power consumption, and a miniaturization of chip and package. In addition non-scalability of Cu pillar/Sn cap or Pb-free solder structure for fine-pitch interconnection leads to the development of bumpless interconnection system. Few bumpless interconnect systems such as BBUL technology, SAB technology, SAM technology, Cu-toCu thermocompression technology, and WOW's bumpless technology using an adhesive have been reviewed in this paper: The key requirements for Cu bumpless technology are the planarization, contamination-free surface, and surface activation.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.1
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• pp.35-43
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• 2017

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.111-114
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• 2002

We propose and fabricate a vertically integrated waveguide thermo-optic switch. It controls the optical path between two vertically stacked waveguide. As a first step, we fabricate polymeric waveguides. The measured propagation loss is ranged from 0.3 db/cm to 0.4 dB/cm at the wavelength of 1.55 $\mu\textrm{m}$. We fabricate the proposed vertically integrated waveguide thermo-optic switch to demonstrate its preliminary feasibility. The measured crosstalk is better than -10 db. The power consumption is about 500 mW. Further effort is necessary to improve its performance.

• Proceedings of the Materials Research Society of Korea Conference
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• 2007.11a
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• pp.55.2-55.2
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• 2007

• Journal of the Korea Society of Computer and Information
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• v.17 no.6
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• pp.1-11
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• 2012

As the process technology scales down, multi-core processors cause serious problems such as increased interconnection delay, high power consumption and thermal problems. To solve the problems in 2D multi-core processors, researchers have focused on the 3D multi-core processor architecture. Compared to the 2D multi-core processor, the 3D multi-core processor decreases interconnection delay by reducing wire length significantly, since each core on different layers is connected using vertical through-silicon via(TSV). However, the power density in the 3D multi-core processor is increased dramatically compared to that in the 2D multi-core processor, because multiple cores are stacked vertically. Unfortunately, increased power density causes thermal problems, resulting in high cooling cost, negative impact on the reliability. Therefore, temperature should be considered together with performance in designing 3D multi-core processors. In this work, we analyze the temperature of the cache in quad-core processors varying cache organization. Then, we propose the low-temperature cache organization to overcome the thermal problems. Our evaluation shows that peak temperature of the instruction cache is lower than threshold. The peak temperature of the data cache is higher than threshold when the cache is composed of many ways. According to the results, our proposed cache organization not only efficiently reduces the peak temperature but also reduces the performance degradation for 3D quad-core processors.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.111-119
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• 2005

Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.595-596
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• 2006

A novel Si via structure is suggested and fabricated for 3D MEMS package using the doped silicon as an interconnection material. Oxide isolations which define Si via are formed simultaneously when fabricating the MEMS structure by using DRIE and oxidation. Silicon Direct Bonding Multi-stacking process is used for stacked package, which consists of a substrate, MEMS structure layer and a cover layer. The bonded wafers are thinned by lapping and polishing. A via with the size of $20{\mu}m$ is fabricated and the electrical and mechanical characteristics of via are under testing.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.2
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• pp.1-12
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• 2021

3D printing, which designs product in three dimensions, draws attention as a technology that will lead the future for it dramatically shortens time for production without assembly, no matter how complex the structure is. The paper studies the latest researches of 3D-printed electronics and introduces papers studied electronics components, power supply, circuit interconnection and 3D-printed PCBs' applications. 3D-printed electronics showed possibility to simplify facilities and personalize electric devices by providing one-stop printing process of electronic components, soldering, stacking, and even encapsulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.570-572
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• 2012

In this paper, a three-dimensional (3-D) low-loss and wide-band BPF based on low-temperature co-fired ceramic (LTCC) has been presented for mm-wave wireless communication applications. The proposed BPF is designed in a 6-layer LTCC substrate. The double patch resonators are fully integrated into the LTCC dielectrics and vertical via and planar CPW transitions are designed for interconnection between embedded resonators and in/output ports and MMICs, respectively. The designed BPF was fabricated in a 6-layer LTCC dielectric. The fabricated BPF shows a centre frequency (fc) of 53.23 GHz and a 3dB bandwidth of 14.01 % from 49.5 to 56.9 GHz (7.46 GHz). An insertion loss of -1.56 dB at fc and return losses below -10 dB are achieved. Its whole size is $4.7{\times}1.7{\times}0.684mm^3$.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.47-52
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• 2008

This investigation was performed in order to study the properties of deposition and layers by Silicon Dioxide, SiO2, as dielectric onto Via and Trench which have high Aspect Ratio (AR). Thus, in order to confirm these properties, three types of CVD, which were PECVD, PETEOS, and ALD, were selected. On the experiment each of the property sections was estimated that step overage of PECVD: <30%, PETEOS: 45%, ALD: 75% and the RSM of PECVD: 27.8 nm, PETEOS: 2.1 nm, ALD: <2.0 nm. As a result of this experiment for the property of electric film, ALD was valuated to be the most favorable outcome. However, ALD was valuated to have the least quality for the deposition rate. ALD deposition rate, $10\;\AA/min$ by $1\;\AA$/1cycle, was prominently lower than PETEOS, which had the deposition rate of $5000\;\AA$/min. Since electric film requires at least $1000\;\AA$ thicknesses, ALD was not suitable for the deposition rate. which is the most important component in a practical use. Therefore, in this particular study, PETEOS was evaluated to be the most suitable recipe.