• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.176-186
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• 2007

An interconnection network can be represented as a graph where a vertex corresponds to a node and an edge corresponds to a link. The diameter of an interconnection network is the maximum length of the shortest paths between all pairs of vertices. The fault diameter of an interconnection network G is the maximum length of the shortest paths between all two fault-free vertices when there are $_k(G)-1$ or less faulty vertices, where $_k(G)$ is the connectivity of G. The fault diameter of an R-regular graph G with diameter of 3 or more and connectivity ${\tau}$ is at least diam(G)+1 where diam(G) is the diameter of G. We show that the fault diameter of a 2-dimensional $m{\times}n$ torus with $m,n{\geq}3$ is max(m,n) if m=3 or n=3; otherwise, the fault diameter is equal to its diameter plus 1. We also show that in $d({\geq}3)$-dimensional $k_1{\times}k_2{\times}{\cdots}{\times}k_d$ torus with each $k_i{\geq}3$, there are 2d mutually disjoint paths joining any two vertices such that the lengths of all these paths are at most diameter+1. The paths joining two vertices u and v are called to be mutually disjoint if the common vertices on these paths are u and v. Using these mutually disjoint paths, we show that the fault diameter of $d({\geq}3)$-dimensional $k_1{\times}k_2{\times}{\cdots}{\times}k_d$ totus with each $k_i{\geq}3$ is equal to its diameter plus 1.

• Journal of electromagnetic engineering and science
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• v.15 no.3
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• pp.185-193
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• 2015

In this paper, a hybrid multiple input multiple output (MIMO) antenna for eight-band mobile handsets is designed and implemented. For the MIMO antenna, two hybrid antennas are laid symmetrically and connected by an interconnection tie, thereby enabling complementary operation. The tie affects both the impedance and radiation characteristics of each antenna. Further, printed circuit board (PCB) embedded type is applied to the antenna design. To verify the results of this study, we designed eight bands-LTE class 12, 13, and 14, CDMA, GSM900, DCS1800, PCS, and WCDMA-and implemented them on a bare board the same size as the real board of a handset. The voltage standing wave ratio (VSWR) is within 3:1 over the entire design band. Antenna isolation is less than -15 dB at the lower band, and -12 dB at the WCDMA band. Envelope correlation coefficient (ECC) of 0.0002-0.05 is obtained for all bands. The average gain and efficiency are measured to range from -4.69 dBi to -2.88 dBi and 33.99% to 51.5% for antenna 1, and -4.74 dBi to -2.97 dBi and 33.45% to 50.49% for antenna 2, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.60-70
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• 1995

As a Basic study to implement a wide-band photonic switching sysetm, we proposed a scheme of free-space-division-multiplexed photonic switching based on a holographic interconnectio method and carried out simple experiments on it. First, we recorded holgraphic interconnection element array for nonblocking optical interconnections. Just a single stage of the array realizes full optical interconnections between NN${\times}$NN input prots and NN${\times}$NN output ports in 3-D space. Next, in reading of the array for optical internnections, we showed that the zeroth-order diffacted beam could be eliminated in the output port by introducing a right angle prism. The elimination of the zeroth-order diffracted beam reduces optical noise in the output ports and provides conveniences of interconnection control in our scheme. Finally, from the experiments on ON-OFF switching of the optical interconnection paths one by one using a spatial (display of the liquid crystal telecision), we showed the feasibility of photonic wsitching based on the holographic interconnection method. We also estimated approximately the maximum interconnectio scale that can be realized without difficulty with current optical devices.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.11 s.114
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• pp.1105-1111
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• 2006

In this paper, using low-temperature co-fired ceramic(LTCC) based system-in-package(SiP) technology, a very compact power amplifier LTCC module was designed, fabricated, and then characterized for 60 GHz wireless transmitter applications. In order to reduce the interconnection loss between a LTCC board and power amplifier monolithic microwave integrated circuits(MMIC), bond-wire transitions were optimized and high-isolated module structure was proposed to integrate the power amplifier MMIC into LTCC board. In the case of wire-bonding transition, a matching circuit was designed on the LTCC substrate and interconnection space between wires was optimized in terms of their angle. In addition, the wire-bonding structure of coplanar waveguide type was used to reduce radiation of EM-fields due to interconnection discontinuity. For high-isolated module structure, DC bias lines were fully embedded into the LTCC substrate and shielded with vias. Using 5-layer LTCC dielectrics, the power amplifier LTCC module was fabricated and its size is $4.6{\times}4.9{\times}0.5mm^3$. The fabricated module shows the gain of 10 dB and the output power of 11 dBm at P1dB compression point from 60 to 65 GHz.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.47-55
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• 1995

Proximity-coupled open-end microstrip interconnections in bilevel planar structures are investigated through three-dimensional finite-difference time-domain(3D-FDTD) method. Three types of EMC (electromagnetically coupled) microstriplines are considered, collinear lines, transverse lines and modified EMC structure. From the analyzed results, it is found that these EMC interconnections have the coupling coefficient enough to interconnect lines in bilevel structures over a broad-band. The computed results of the modified EMC structure was compared with measurement from physical model and the computed results of via hole interconnection.

• Journal of IKEEE
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• v.17 no.2
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• pp.176-181
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• 2013

This paper presents a CMOS impulse radio ultra-wideband (IR-UWB) receiver implemented using IBM 0.13um CMOS technology for inner/inter-chip wireless interconnection. The IR-UWB receiver is based on the non-coherent architecture which removes the complexity of RF architecture (such as DLL or PLL) and reduces power consumption. The receiver consists of three blocks: a low noise amplifier (LNA) with active balun, a correlator, and a comparator. Simulation results show the die area of the IR-UWB receiver of 0.2mm2, a power gain (S21) of 12.5dB, a noise figure (NF) of 3.05dB, an input return loss (S11) of less than -16.5dB, a conversion gain of 18dB, a NFDSB of 22. The receiver exhibits a third order intercept point (IIP3) of -1.3dBm and consumes 22.9mW of power on the 1.4V power supply.

• Journal of the Korean Society for Precision Engineering
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• v.29 no.12
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• pp.1376-1381
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• 2012

Optical devices are used extensively in the field of information network. Increasing demand for optical device, optical interconnection has been a important issue for commercialization. However many problems exist in the interconnection between optical device and optical fiber, and in the case of the multi-channel, problems of the optical alignment and optical array arise. For solving the alignment and array problem of optical device and the optical fiber, we fabricated fiber alignment and array by using imprint technology. Achieved higher precision of optical fiber alignment and array due to fabricating using imprint technology. The silicon stamp with different depth was fabricated using the conventional photolithography. Using the silicon stamp, a nickel stamp was fabricated by electroforming process. We conducted imprint process using the nickel stamp with different depth. The optical alignment and array by fabricating the patterns of optical device and fiber alignment and array using imprint process, and achieved higher precision of decreasing the dimensional error of the patterns by optimization of process. The fabricated optical interconnection of PLC device was measured 3.9 dB and 4.2 dB, lower than criteria specified by international standard.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.113-120
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• 2010

Even networks were introduced as a class of fault-tolerant multiprocessor networks and analyzed so many useful properties and algorithms such as simple routing algorithms, maximal fault tolerance, node disjoint path. Introduced routing algorithms and node disjoint path algorithms are proven to be optimal. However, it has not been introduced to constructing scheme for edge-disjoint spanning trees in even networks. The design of edge-disjoint spanning trees is a useful scheme to analyze for measuring the efficiency of fault tolerant of interconnection network and effective broadcasting. Introduced routing algorithm or node disjoint path algorithm are for the purpose of routing or node disjoint path hence they are not applicable to constitute edge disjoint spanning tree. In this paper, we show a construction algorithm of edge-disjoint spanning trees in even network $E_d$.

• Journal of the Korean Society for Nondestructive Testing
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• v.34 no.6
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• pp.441-446
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• 2014

A 3D ultrasound image is desired in many medical examinations. However, the implementation of a 2D array, which is needed for a 3D image, is challenging with respect to fabrication, interconnection and cabling. A 2D sparse array, which needs fewer elements than a dense array, is a realistic way to achieve 3D images. Because the number of ways the elements can be placed in an array is extremely large, a method for optimizing the array configuration is needed. Previous research placed the target point far from the transducer array, making it impossible to optimize the array in the operating range. In our study, we focused on optimizing a 2D sparse array transducer for 3D imaging by using a simulated annealing method. We compared the far-field optimization method with the near-field optimization method by analyzing a point-spread function (PSF). The resolution of the optimized sparse array is comparable to that of the dense array.