• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.262-263
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• 2007

In this paper, fully embedded and miniaturized diplexer has been designed, fabricated, and characterized for dual-band/mode CDMA handset applications. The size of the embedded diplexer is significantly reduced by embedding high Q circular spiral inductors and high DK MIM capacitors into low cost organic package substrate. The fabricated diplexer has insertion losses and isolations of -0.5 and -23dB at 824-894MHz and -0.7 and -22dB at 1850-1990MHz, respectively. Its size is 3.9mm$\times$3.9mm$\times$ 0.77mm (height). The fabricated diplexer is the smallest one which is fully embedded into low cost organic package substrate.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.6
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• pp.293-297
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• 2021

This paper presents how to create a 3D map and solve problems related to generating a global path planning for navigation. Map creation and localization were performed using the RTAB-Map package to create a 3D map of the environment. In addition, when the target point is within the obstacle space, the problem of not generating a global path was solved using the asr_navfn package. The performance of the proposed system is validated through experiments with a wheelchair-type robot.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.687-698
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• 2001

This paper presents a three dimensional stacked pad area away (PAA) package configuration as an implementation method of radio frequency (RF) circuits. 224MHz RF circuits of intelligence traffic system(ITS) were constructed with the stacked PAA RF pakage configuration. In the process of manufacturing the stacked PAA RF pakage, RF circuits were partitioned to subareas following their function and operating frequency. Each area of circuits separated to each subunits. The operating characteristics of RF PAA package module and the electrical properties of each subunits were examined. The measurement of electrical parameters for solder balls which were interconnects for stacked PAA RF packages showed that the parasitic capacitance and inductance were 30fF and 120pH, respectively, which might be negligible in PAA RF packaging system. HP 4396B network/spectrum analyzer revealed that the amplification gain of a receiver and transmitter at 224 MHz was 22dB and 27dB, respectively. The gain was 3dB lower than designed values. The difference was probably generated from fabrication process of the circuits by employing commercial standard

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.17-20
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• 2003

The EMC's rheological effects on molding process are evaluated in this study. When considering mold processing for IC packages, the major concerning items in current studies are incomplete fill, severe wire sweeping and paddle shifts etc. To simulate EMC's fast curing rheokinetics with 3D mold flow behavior, one should select appropriate rheometry which characterize each EMC's rheological motion and finding empirical parameters for numerical analysis current studies present the new rheometry with parallel plate rheometry for reactive rheokinetic experiments, the experiment and numerical analysis is done with the commercial higher filler loaded EMC for the case of Thin Quad Plant Packages (TQFP) with package thickness below 1.0 mm. The experimental results and simulation results based on new rheometry matches well in point of the prediction of wire sweep, filling behavior of melt front advancement and void trapping position.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.323-330
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• 2005

We fabricate PIN PD (Positive Intrinsic Negative Photo-Diode) for CWDM optical repeater and optical transmission system, and analyze theoretically the characteristics to verify the capability of device fabricated. Furthermore, we integrate CWDM filter into PD package to enhance the cost and the performance when compared to the conventional system, in which CWDM filter and PD package are linked by optical fusion splicing. The integrated CWDM PD is fabricated by three steps as follows: CWDM filter design, PD packaging, and product assembly and test. The results of measurement for PD fabricated reveal 0.5 dB bandwidth of 17 nm, isolation over 60 dB at transmission port and over 20 dB at reflection port. Also, the IMD3 for wireless communication is over 63 dBc, and the responsivity of PD presents over 0.9 A/W for 20 samples of the total 23 PD. The total insertion loss reduces about 0.4${\~}$0.7 dB due to the integrated assembly of CWDM and PD.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.1
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• pp.35-43
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• 2017

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.7 no.1
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• pp.47-52
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• 2008

We present a 3-D profiler specially devised for the profile measurement of rough surfaces that are difficult to be measured with conventional non-contact interferometer. The profiler comprises multiple two-point-diffraction sources made of single-mode optical fibers. Test measurement proves that the proposed profiler is well suited for the warpage inspection of microelectronics components with rough surface, such as unpolished backsides of silicon wafers and plastic molds of integrated-circuit chip package.

• Journal of Power System Engineering
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• v.18 no.1
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• pp.32-37
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• 2014

In this study, the optimum design process of an indoor package air-conditioner (PAC) was implemented by Taguchi method. The goal of this study is to obtain the best set condition of each control factor composing of an indoor PAC. The number of revolution of a double inlet sirocco fan installed in an indoor PAC was measured by the orthogonal array of $L_{18}(2^3{\times}3^4)$ and analysed by using the-smaller- the-better characteristic among the static characteristic analyses. As a result, the optimum condition of an indoor PAC was found as a set of when the cost of production, assembling and working conditions were considered. Moreover, the number of revolution of a double-inlet sirocco fan used for an optimum condition was reduced about 8.5% more than that of a standard condition for the target flowrate of $18.5m^3/min$.