• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.262-263
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• 2007

In this paper, fully embedded and miniaturized diplexer has been designed, fabricated, and characterized for dual-band/mode CDMA handset applications. The size of the embedded diplexer is significantly reduced by embedding high Q circular spiral inductors and high DK MIM capacitors into low cost organic package substrate. The fabricated diplexer has insertion losses and isolations of -0.5 and -23dB at 824-894MHz and -0.7 and -22dB at 1850-1990MHz, respectively. Its size is 3.9mm$\times$3.9mm$\times$ 0.77mm (height). The fabricated diplexer is the smallest one which is fully embedded into low cost organic package substrate.

• 대한임베디드공학회논문지
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• 제16권6호
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• pp.293-297
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• 2021

This paper presents how to create a 3D map and solve problems related to generating a global path planning for navigation. Map creation and localization were performed using the RTAB-Map package to create a 3D map of the environment. In addition, when the target point is within the obstacle space, the problem of not generating a global path was solved using the asr_navfn package. The performance of the proposed system is validated through experiments with a wheelchair-type robot.

• 대한전자공학회논문지SD
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• 제38권10호
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• pp.687-698
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• 2001

본 논문에서는 RF(Radio Frequency) 회로의 구현 방법으로서 3차원 적층형태의 PAA(Pad Area Array) 패키지 구조를 제시하였다. 지능 교통망 시스템(Intelligence Traffic System)을 위한 224㎒의 RF 시스템을 적층형 PAA 패키지 구조에 적용시켜 구현하였다. 적층형 PAA 패키지 구성 과정에서는 RF 회로를 기능별, 주파수별로 분할하였고 3차원적인 적층형태의 PAA 구조로 설계한 후 분할된 단위 모듈의 RF 동작특성과 3차원 적층형 PAA 패키지 모듈의 전기적 특성을 개별적으로 분석하였다. 적층형 PAA RF 패키지가 갖는 연결단자인 공납(Solder Ball)에 대한 전기적 파라미터 측정결과 그 전기적 특성인 기생 캐패시턴스와 기생 인덕턴스는 각각 30fF, 120pH로 매우 미세하여 PAA 패키지 구조인 RF 시스템에 끼치는 영향이 무시될 수 있음을 확인하였고, 구성된 송수신단은 HP 4396B network/spectrum analyser로 측정한 결과 224㎒에서 수신단, 송신단 증폭이득은 각각 22dB 27dB. 나타나서 설계값에 비하여 3dB감소 된 것을 알 수 있었다. 이는 설계와 제작과정 사이의 차이로 판명되었으며 수동부품 보정방법을 통하여 각 단위모듈의 입출력 임피던스 정합을 이루어 각각 24dB, 29dB로 개선시킬 수 있었다. 따라서, 본 실험에서는 RF 회로를 기능별로 모듈화하고 3차원 적층형 PAA 패키지 구조로 구현하여 전기적 특성을 개선시킬 수 있음을 확인하였다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.17-20
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• 2003

The EMC's rheological effects on molding process are evaluated in this study. When considering mold processing for IC packages, the major concerning items in current studies are incomplete fill, severe wire sweeping and paddle shifts etc. To simulate EMC's fast curing rheokinetics with 3D mold flow behavior, one should select appropriate rheometry which characterize each EMC's rheological motion and finding empirical parameters for numerical analysis current studies present the new rheometry with parallel plate rheometry for reactive rheokinetic experiments, the experiment and numerical analysis is done with the commercial higher filler loaded EMC for the case of Thin Quad Plant Packages (TQFP) with package thickness below 1.0 mm. The experimental results and simulation results based on new rheometry matches well in point of the prediction of wire sweep, filling behavior of melt front advancement and void trapping position.

• 마이크로전자및패키징학회지
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• 제12권4호통권37호
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• pp.323-330
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• 2005

저밀도 파장분할 방식 (CWDM)을 사용하는 광중계기와 광전송시스템에 사용할 수 있는 PIN PD (Positive Intrinsic Negative Photo Diode)를 제작하고 특성을 알아보았다. 특별히 제작된 CWDM 필터를 PD 패키지에 포함하여 일체형으로 제작하여 기존에 별도로 연결하여 사용하던 방법에 비해 작업성과성능 그리고 가격면에서 우수함을 보였다. 일체형 저밀도 파장분할 PD를 제작하기 위해서 CWDM 필터 조립 단계, PD 패키징 단계, 완제품 최종 조립 및 측정 단계의 3단계 과정을 수행하였다. 제작된 PD는 0.5 dB 대역폭이 17 nm, 투과 단자의 인접채널의 고립도는 60 dB 이상으로 측정되었고, 반사 단자의 고립도는 20 dB 이상으로 측정되었다. 무선주파수 특성을 위해 IMD3를 측정결과 63dBc 이상이었으며 PD의 응답도는 제작 샘플 23개중 20개가 0.9A/W 이상이었다. 일체형으로 제작함으로써 전체적인 삽입손실이 0.4-0.7 dB 정도 줄었다.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• 한국전기전자재료학회논문지
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• 제16권12S호
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• 마이크로전자및패키징학회지
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• 제24권1호
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• pp.35-43
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• 2017

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

• 한국기계가공학회지
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• 제7권1호
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• pp.47-52
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• 2008

We present a 3-D profiler specially devised for the profile measurement of rough surfaces that are difficult to be measured with conventional non-contact interferometer. The profiler comprises multiple two-point-diffraction sources made of single-mode optical fibers. Test measurement proves that the proposed profiler is well suited for the warpage inspection of microelectronics components with rough surface, such as unpolished backsides of silicon wafers and plastic molds of integrated-circuit chip package.

• 동력기계공학회지
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• 제18권1호
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• pp.32-37
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• 2014

In this study, the optimum design process of an indoor package air-conditioner (PAC) was implemented by Taguchi method. The goal of this study is to obtain the best set condition of each control factor composing of an indoor PAC. The number of revolution of a double inlet sirocco fan installed in an indoor PAC was measured by the orthogonal array of $L_{18}(2^3{\times}3^4)$ and analysed by using the-smaller- the-better characteristic among the static characteristic analyses. As a result, the optimum condition of an indoor PAC was found as a set of when the cost of production, assembling and working conditions were considered. Moreover, the number of revolution of a double-inlet sirocco fan used for an optimum condition was reduced about 8.5% more than that of a standard condition for the target flowrate of $18.5m^3/min$.