• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.51-57
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• 2015

In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.5 no.2
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• pp.36-41
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• 2006

This study was carried out to install the lifting force of a two hinge type stand mechanism by 6 Sigma process in advance. This unit is designed for the display device in order to enhance the ergonomics for effective height adjustment and maintenance at any preferred position. The unit will be very useful for the mechanism fabricated with coil springs and disc springs as a torque generator. The 6 Sigma process was applied to select two key factors among 7 elements to lift the head unit and to find out applicable tolerance securing the 3.4 ppm of defects as well as what deviation of lifting force we can expect between calculation and experiment at the design stage of development. The result of this study can be applied to various units for the optimization of the smooth lift.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.818-821
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• 2010

본 논문에서는 차량 레이더 시스템용 시그마-델타 변조기를 제안한다. 개발된 변조기는 차량 레이더 시스템에서 고주파 대역 신호의 고해상도 데이터 변환, 즉 아날로그-디지털변환을 수행하는데 사용되며 저전압 및 저 왜곡 특성을 가진 몸체효과 보상형 스위치 구조로 구현되어 있다. 제안된 변조기는 0.25 마이크론 이중 폴리 3-금속 표준 CMOS 공정으로 제작되었고, $1.9{\times}1.5mm^2$의 다이 면적을 점유한다. 제안된 회로는 2.7V의 동작 전압에서 기존의 부트스트랩형 회로보다 약 20dB 향상된 우수한 총 고조파 왜곡 특성을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.65-73
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• 2007

This paper presents a low power CMOS continuous-time $\Sigma\Delta$ (sigma-delta) modulator for UMTS receivers. The loop filter of the continuous-time $\Sigma\Delta$ modulator consists of an active-RC filter which performs high linearity characteristics and has a simple tuning circuit for low power operating system The architecture of this modulator is the $3^{rd}-order$ 4-bit single loop configuration with a 24 of OSR (Oversampling Ratio) to increase the power efficiency. The modulator includes a half delay feedback path to compensate the excess loop delay. The experimental results of the modulator are 71dB, 65dB and 74dB of the peak SNR, peak SMR and dynamic range, respectively. The continuous-time $\Sigma\Delta$ modulator is fabricated in a 0.18-um 1P4M CMOS standard process and dissipates 15mW for a single supply voltage of 1.8V.

• Analytical Science and Technology
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• v.12 no.3
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• pp.235-242
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• 1999

It is impossible to measure the fraction of the precipitates which are neither plenty nor distiguishable on micrographs, using point counting method or image analyzer. In this study, phase fraction of sigma, carbide and boride which are important to mechanical properties of Ni base superalloy Udimet 720 has been measured using a quantitative X-ray diffraction technique combined with electrochemical extraction. The alloys had been exposed at $800^{\circ}C$ for various times up to 3000 hours to have a variation of the amount of the minor precipitates. The amount of sigma had increased exponentially with increasing exposure time up to 3000 hours before saturation. It can be argued that the finishing point of precipitation is around 5000 hours and maximum amount of sigma to be produced is about 5% in weight. The amounts of $M_{23}C_6$ and $M_3B_2$ were maintained constant at the level of 0.1~0.5% in weight, regardless of exposure time.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• Information Systems Review
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• v.8 no.3
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• pp.245-259
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• 2006

In order to utilize BSC as an operational tool for communicating strategies across the hierarchies of the organization, a growing number of companies have tried to link BSC processes with other PI tools. Company D has carried out the SEM project to identify the causal structure between innovation activities and performance management in 2005 and 2006. The company synthesizes BSC and 6 Sigma methodologies at the BU level, and the new process made it possible to manage performances and make decision more "realistic" on the basis of information technologies. We expect that this study provide organizations, which have difficulties streamlining the performance management processes at the strategic level and those of operational level, with implications for realizing more "execution-oriented" RTE.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.189-196
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• 2010

In this paper, we proposed the adaptive local sigma filter reducing noises generated by an image sensor. The small noises generated by the image sensor are amplified by increased an analog gain and an exposure time of the image sensor together with information. And the goal of this work was the system design that is reduce the these amplified noises. Edge data are extracted by Flatness Index Map algorithm. We made the threshold adaptively changeable by the luminance average in this algorithm that extracts the edge data not in high luminance, but just low luminance. The Local Sigma Filter performed only about the edge pixel that were extracted by Flatness Index Map algorithm. To verify the performance of the designed filter, we made the Window test program. The hardware was designed with HDL language. We verified the hardware performance of Local Sigma Filter system using FPGA Demonstration board and HD image sensor, $1280{\times}720$ image size and 30 frames per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.25-33
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• 2007

In this paper, a fourth-order single-bit delta-sigma modulator is presented and implemented. The loop-filter is composed of both feedback and feedforward paths. Measurement results show that maximum 99dB dynamic range is achievable at a clock rate of 3.2MHz for 20kHz baseband. The proposed modulator has been fabricated in a $0.18{\mu}m$ standard CMOS process.

• Journal of the Korea Safety Management & Science
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• v.8 no.4
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• pp.239-247
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• 2006

This paper is to propose new features and models for process innovation after classifying in three categories ; conventional six sigma, lean six sigma and 3rd generation six sigma. First considering two project types which are bottom-up and tod-down, DMAIC process is linked up with QC story 15 steps. Secondly, I present Koreanized lean six sigma model using Japanese production technology and principles. Lastly, this paper also depicts a new 3rd generation six sigma model utilizing MBNQA management quality system.