• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.157-165
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• 2013

In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

• Journal of the Korean Society of Marine Environment & Safety
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• v.5 no.2
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• pp.99-111
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• 1999

The object of this study is to get the superior double hull structure to its crashworthiness against collision comparing absorbed energy capacities of its various types with each other, varying material properties, collision positions and velocities, and structural arrangements such as double hull width, web and stringer spaces, etc. Local absorbed energy capacities, failure behaviors and damage extents of their members are also considered during collision in addition to the estimations of their global ones. This paper describes a series of numerical simulations of collisions between DWT 45,000 oil tanker(struck ship) and DWT 10,500 rigid one(striking ships) using Hydrocode LS/DYNA3D. Collisions are assumed to occur at the middle of struck ship with striking one moving at right angle to its centerline. The following remarks were obtained through this study: More flexible the double hull structure is, much superior its crashworthiness against collision is. The increment of double hull width does not give much influence than other factors do. The exact use of material property such as failure strain is also important on the numerical simulation of collision.

• Journal of the Society of Naval Architects of Korea
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• v.44 no.2 s.152
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• pp.166-173
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• 2007

Collision analysis problems between ship to ship can be generally classified into the external mechanics(outer dynamics) and internal mechanics(inner dynamics). The former can be also dealt with the concept of fluid-structure interaction and the use of rigid body dynamic program, depending on the ways handling the hydrodynamic pressure due to surrounding water. In this study, full scale ship collision simulation was carried out, such as a DWT 75,000 ton striking ship collided at right angle to the middle of a DWT 150,000 struck ship with 10 knots velocity, coupling MCOL, a rigid body mechanics program for modeling the dynamics of ships, to hydrocode LS-DYNA. It could be confirmed that more suitable damage estimation would be performed in the case of the collision simulations with consideration of surrounding water through the comparison with the collision simulation results of fixed struck ships without it. Through this study, the opportunity could be obtained to establish a more effective ship collision simulation technique between ship to ship.

• Journal of the Society of Naval Architects of Korea
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• v.36 no.4
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• pp.87-94
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• 1999

Empirical design is still used to avoid a structural damage because impact phenomenon and structural behaviour due to wave impact load can not examined accurately. The damage due to wave impact load is largely affected by impact pressure impulse and impact load area. The objective of this study is, as the second step, to develop an efficient scantling program of bow flare structure, and to predict its impact load area by comparing maximum dented deformations at center of idealized panel structure model of bow flare structure of 300k DWT VLCC using LS/DYNA3D code, which will be used for its verification of dynamic structural analysis, as the next step. Through this study, the impact load area was estimated as $1.5s{\times}1.5s$ stiffener space(s) in the case of panel with stiffeners and as $2.5s{\times}2.5s$, with stringers, under impact pressure curve with peak height 6.5MPa, tail height 1.0MPa, and duration time 5.0msec.

• Journal of Advanced Marine Engineering and Technology
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• v.32 no.8
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• pp.1309-1314
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• 2008

Seismic data is often contaminated with high-energy, spatially aliased noise, which has proven impractical to attenuate using Fourier techniques. Wavelet filtering, however, has proven capable of attacking several types of localized noise simultaneously regardless of their frequencies. In this study a 2-D stationary wavelet transform is used to decompose seismic data into its wavelet components. A threshold is applied to these coefficients to attenuate high amplitude noise, followed by an inverse transform to reconstruct the seismic trace. The stationary wavelet transform minimizes the phase-shift errors induced by thresholding that occur when the conventional discrete wavelet transform is used.

• Journal of the Society of Naval Architects of Korea
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• v.37 no.1
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• pp.99-110
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• 2000

The damages due to wave impact loads are largely affected by impact pressure impulse and impact load area. The objective of this study is, as the third step, to perform dynamic structural analysis of bow flare structure of 300,000 DWT VLCC using LS/DYNA3D code, and to verify its dynamic structural behaviors. The impact load areas of stiffener space $1.5s{\times}1.5s$ and $2.5s{\times}2.5s$ are applied to bow flare structure part with relatively flexible stiffeners, and with stiff members such as stringers, webs etc., respectively, under the wave impact load with peak height 6.5MPa, tail 1.0MPa, and duration time 5.0msec. Through the dynamic structural analysis in this study, it might be thought that the structural strength of bow flare structure is generally sufficient for these wave impact load and areas, except that large damages were found at bow flare structure area with flexible wide span stiffeners.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.29-38
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• 2009

In this paper, a high performance pipelined computing design of parallel multiplier-temporal buffer-parallel accumulator is present for the convolution-based non-cascaded architecture aiming at the real time Discrete Wavelet Transform(DWT) processing. The convolved multiplication of DWT would be reduced upto 1/4 by utilizing the filter coefficients symmetry and the up/down sampling; and it could be dealt with 3-5 times faster computation by LUT-based DA multiplication of multiple filter coefficients parallelized for product terms with an image data. Further, the reutilization of computed product terms could be achieved by storing in the temporal buffer, which yields the saving of computation as well as dynamic power by 50%. The convolved product terms of image data and filter coefficients are realigned and stored in the temporal buffer for the accumulated addition. Then, the buffer management of parallel aligned storage is carried out for the high speed sequential retrieval of parallel accumulations. The convolved computation is pipelined with parallel multiplier-temporal buffer-parallel accumulation in which the parallelization of temporal buffer and accumulator is optimize, with respect to the performance of parallel DA multiplier, to improve the pipelining performance. The proposed architecture is back-end designed with 0.18um library, which verifies the 30fps throughput of SVGA(800$\times$600) images at 90MHz.

• Journal of Information Processing Systems
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• v.13 no.2
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• pp.340-347
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• 2017

A watermark is a signal added to the original signal in order to preserve the copyright of the owner of the digital content. The basic challenge for designing a watermarking system is a dilemma between transparency and robustness. If we want a higher rate of transparency, there has to be a compromise in terms of its robustness and vice versa. Also, until now, watermarking is generalized, resulting in the need for a specialized algorithm to work for a specialized image processing application domain. Our proposed technique takes into consideration the image characteristics for watermark insertion and it optimizes transparency and robustness. It achieved a 99.98% retrieval efficiency for an image blurring attack and counterfeits other attacks. Our proposed technique counterfeits almost all of the image processing attacks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2C
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• pp.130-138
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• 2006

In this paper, a new stereo image watermarking scheme based-on adaptive disparity estimation algorithm is proposed. That is, a watermark image is embedded into the right image of a stereo image pair by using the DWT and disparity information is extracted from this watermarked right image and the left image. And then, both of this extracted disparity information and the left image are transmitted to the recipient through the communication channel. At the receiver, the watermarked right image is reconstructed from the received left image and disparity information through an adaptive matching algorithm. a watermark image is finally extracted from this reconstructed right image. From some experiments using CCETT's 'Manege' and 'Friends' images as a stereo image and English alphabet '3DRC' as a watermark image, it is found that the PSNRs of the watermarked image from the reconstructed right images through the adaptive matching algorithm & DWT is improved 2.03 dB, 3.03 dB and robusted against various attacks. These experimental results also suggest a possibility of practical implementation of an adaptive matching also-rithm-based stereo imagewatermarking scheme proposed in this paper.