• Title/Summary/Keyword: 2-step Gate

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Parameter Calibration and Sensitivity Analysis for Numerical Modeling of Flow and Bed Changes near the Opening Gate for Sediment Release (배사구 유입부 흐름 및 하상변동 수치모의를 위한 매개변수 검정 및 민감도 분석에 관한 연구)

  • Jang, Eun-Kyung;Lim, Jong-Chul;Ji, Un;Yeo, Woon-Kwang
    • Journal of Environmental Science International
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    • v.20 no.9
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    • pp.1151-1163
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    • 2011
  • The bed change analysis near the opening gate of a dam or weir to release deposited sediments have been conducted mostly using the numerical models. However, the use of unverified input parameters in the numerical model is able to produce the different results with natural and real conditions. Also, the bed changes near the opening gate of a dam or weir calculated with a numerical model could be varied depending on the geometry extent included the downstream area with supercritical flow in the model. In addition, the different time steps could provide different results in the bed change calculation, even though other conditions such as input parameters, geometries, and total simulation time were same. Therefore, in this study, hydraulic experiments were performed to validate the eddy viscosity coefficient which is the one of important input parameters in the RMA2 model and relevant to variation of simulation results. The bed changes were calculated using the SED2D model based on flow results calculated in the RMA2 model with the verified and selected eddy viscosity coefficient and also compared with experimental results. The bed changes near the opening gate were underestimated in the numerical model comparing with experimental results except only the numerical case without the modeling section of sediment release pipe and downstream area where the supercritical flow was produced. For the simulation of minimum time steps, different shapes of scour hole were produced in numerical and physical modeling.

Optimal Control of Injection Molding Process by Using temperature Sensor (캐비티 온도센서를 이용한 최적 사출공정 제어)

  • Park, Cheon-Soo;Kang, Chul-Min
    • Design & Manufacturing
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    • v.2 no.5
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    • pp.30-33
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    • 2008
  • Injection Molding is the most effective process for mass production of plastic parts. The injection molding process is composed with several steps such as Filling, Packing, Holding, Cooling, Ejecting. Among them, filling and packing process should be considered carefully to improve accuracy of dimension, surface quality of plastic parts. Usually the quality above-mentioned is managed with weight of part after molding on the field. In this paper, a series of experiment for molding automotive front bumper was conducted with cavitity temperature sensor to optimize switch-over time(V-P switching), hot runner vale gate sequence time during filling and packing step for the purpose of uniform quality, weight at every molding. As a result, it was found that it is effective method to use temperature sensor in injection molding for quality control of plastic molding.

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Development of the Digital Controller for High Precision Digital Power Supply (고정밀전원장치를 위한 디지털 제어기 개발)

  • Ha, K.M.;Lee, S.K.;Kim, Y.S.
    • Proceedings of the Korean Society of Marine Engineers Conference
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    • 2006.06a
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    • pp.249-250
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    • 2006
  • In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

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RTN과 Wet Oxidation에 의한 $Ta_2O_5$의 전기적 특성의 최적화

  • 정형석;임기주;양두영;황현상
    • Proceedings of the Korean Vacuum Society Conference
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    • 2000.02a
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    • pp.104-104
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    • 2000
  • MOS소자의 크기가 작아짐에 따라 gate 유전막의 두께 또한 얇아져야 한다. 두께가 얇아짐에 따라 gate 유전막으로써 기존의 SiO2는 direct tunneling으로 인해 높은 누설전류를 수반한다. 그래서 높은 유전상술르 가지는 물질들에 대한 연구의 필요성이 대두되고 있다. 그중 CVD-Ta2O5는 차세대 MOSFET소자기술에 있어서 높은 유전상수($\varepsilon$r+25)와 우수한 step coverage 때문에 각광을 받고 있는 물질중에 하나이다. 본 연구에서는 Ta2O5를 gate를 유전막으로 사용하고 RTN처리와 wet oxidation을 접목시켜 이들의 전기적인 특성을 향상시킬 수 있었다. p-형 wafer 위에 D2와 O2를 사용하여 SiO2(100 )를, NH3를 이용하여 Nitridation(10 )을 전처리로써 각각 실시하였고 그 위에 MOCVD방법으로 Ta2O5를 80 성장시켰다. 첫 번째 시편은 45$0^{\circ}C$ 10min동안 wet oxidation을 시켰고, 두 번째 시편은 $700^{\circ}C$ 60sec동안 NH3 분위기에서 RTN 처리를 하였다. 세 번째 시편은 동일조건으로 RTN 처리후 wet oxidation을 하였다. 그 후 각각의 시편을 capacitor를 제작하고 그 전기적 특성을 관찰하였다. Wet oxidation만을 시킨 시편은 as-deposited Ta2O5 시편에 비해서 -1.5V에서 누설전류는 약 2~3 order정도 감소되었고 accumulation 영역에서의 capacitance 값은 oxide층의 성장(5 )을 무시하면 거의 변화하지 않았다. RTN처리만 된 시편의 경우는 -1.5V에서 누설전류는 2~3order 정도 증가되었지만, accumulation 영역에서 capacitance 값은 거의 2qwork 증가하였다. 이 두가지 공정을 접목시킨 즉 RTN 처리후 wet oxidation 처리된 시편의 경우는 as-deposited Ta2O5 시편에 비해서 -1.5V에서 누설전류는 1 order 정도 감소하였고, accumulation 지역에서의 capacitance 값은 약 2배 증가하였다. 즉 as deposited Ta2O5 시편의 accumulation 지역의 capacitance 값은 12.8 fF/um2으로써 그 유효두께는 27.0 이었지만, RTN 처리후에 wet oxidation 시킨 시편의 accumulation 지역의 capacitance값은 21.2fF/um2으로써 그 유효두께는 16.3 이 되었다. 결론적으로 as deposited Ta2O5 시편에 RTN 처리후 wet oxidation을 실시한 결과 capacitance 값이 약 2배정도 증가하였고 누설전류는 약 1 order 정도 감소됨을 확인하였다.

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Proposed Efficient Architectures and Design Choices in SoPC System for Speech Recognition

  • Trang, Hoang;Hoang, Tran Van
    • Journal of IKEEE
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    • v.17 no.3
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    • pp.241-247
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    • 2013
  • This paper presents the design of a System on Programmable Chip (SoPC) based on Field Programmable Gate Array (FPGA) for speech recognition in which Mel-Frequency Cepstral Coefficients (MFCC) for speech feature extraction and Vector Quantization for recognition are used. The implementing process of the speech recognition system undergoes the following steps: feature extraction, training codebook, recognition. In the first step of feature extraction, the input voice data will be transformed into spectral components and extracted to get the main features by using MFCC algorithm. In the recognition step, the obtained spectral features from the first step will be processed and compared with the trained components. The Vector Quantization (VQ) is applied in this step. In our experiment, Altera's DE2 board with Cyclone II FPGA is used to implement the recognition system which can recognize 64 words. The execution speed of the blocks in the speech recognition system is surveyed by calculating the number of clock cycles while executing each block. The recognition accuracies are also measured in different parameters of the system. These results in execution speed and recognition accuracy could help the designer to choose the best configurations in speech recognition on SoPC.

Study of dry etch characteristic of TiN thin film for metal gate electrode in MIM capacitor (MIM 커패시터의 Metal 게이트 전극을 위한 TiN 박막의 건식 식각 연구)

  • Park, Jeong-Su;Ju, Yeong-Hui;Woo, Jong-Chang;Heo, Gyeong-Mu;Wi, Jae-Hyeong;Kim, Chang-Il
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2009.10a
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    • pp.219-220
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    • 2009
  • 이번 실험에서는 TiN의 건식 식각 특성을 연구하기 위해 $BCl_3/Ar/N_2$ 유도 결합플라즈마를 이용하였다. BCl3와 Ar의 가스 비율이 $BCl_3$ (5 sccm)/Ar (15 sccm)/N (4 sccm) 인 상황에서 RF power와 DC bias, 그리고 process pressure을 식각변수로 설정하였다. TiN의 식각률은 Alpha-step 500으로 측정하였고 표면의 식각 후 화학반응은 XPS로 측정하였다.

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A Study on the Silicon Nitride for the poly-Si Thin film Transistor (다결정 박막 트랜지스터 적용을 위한 SiNx 박막 연구)

  • 김도영;김치형;고재경;이준신
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.12S
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    • pp.1175-1180
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    • 2003
  • Transformer Coupled Plasma Chemical Vapor Deposited (TCP-CVD) silicon nitride (SiNx) is widely used as a gate dielectric material for thin film transistors (TFT). This paper reports the SiNx films, grown by TCP-CVD at the low temperature (30$0^{\circ}C$). Experimental investigations were carried out for the optimization o(SiNx film as a function of $N_2$/SiH$_4$ flow ratio varying ,3 to 50 keeping rf power of 200 W, This paper presents the dielectric studies of SiNx gate in terms of deposition rate, hydrogen content, etch rate and leakage current density characteristics lot the thin film transistor applications. And also, this work investigated means to decrease the leakage current of SiNx film by employing $N_2$ plasma treatment. The insulator layers were prepared by two step process; the $N_2$ plasma treatment and then PECVD SiNx deposition with SiH$_4$, $N_2$gases.

Effect of Net-Step Exercise on Gait Ability, Depression, Cognitive Function and Activities of Daily Living in Older Adults (Net-Step Exercise가 노인의 보행기능, 우울, 인지기능 및 일상생활 수행능력에 미치는 영향)

  • Lee, Eun Ja;Yoo, Jae Boone
    • The Korean Journal of Rehabilitation Nursing
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    • v.19 no.2
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    • pp.108-117
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    • 2016
  • Purpose: This study aimed to prove the effects of the net-step exercise (NSE) on gait ability, depression, cognitive function and activities of daily living (ADL) in older adults. Methods: The study employed a non-equivalent control group non-synchronized design. A total of 64 community-dwelling older adults were recruited and divided equally into two groups; 32 subjects for an experimental group and 32 subjects for a control group. In the experimental group, the NSE was applied to an hour, two times per week for 4 weeks. The level of gait ability, depression, cognitive function and ADL were measured before and after NSE. The study conducted from July to August, 2016. Data were analyzed with descriptive statistics, $x^2$ test, Fisher's exact test, t-test, ANCOVA, and Pearson correlation coefficients using SPSS/WIN 22.0 version. Results: Gait ability, depression, cognitive function were significantly better in the experimental group than the control group. However, the difference in ADL was not significant between the two groups. Conclusion: These findings in this study showed that the NSE was an efficient intervention for older adults. Nurses could apply non-pharmacological interventions to avoid pharmacological side-effects.

Numerical Simulation of Dam Break Flow using EFDC Model and Parameter Sensitivity Analysis (EFDC 모형을 이용한 댐 붕괴류 수치모의 및 매개변수 민감도 분석)

  • Jang, Chul;Song, Chang Geun
    • Journal of the Korean Society of Safety
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    • v.31 no.4
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    • pp.143-149
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    • 2016
  • In this study, a series of numerical simulation of dam break flow was conducted using EFDC model, and input conditions including cell size, time step, and turbulent eddy viscosity were considered to analyze parameter sensitivity. In case of coarse mesh layout, the propagated length of the shock wave front was ${\Delta}_x$ longer than that of other mesh layouts, and the velocity results showed jagged edge, which can be cured by applying fine grid mesh. Turbulent eddy viscosity influenced magnitude of the maximum velocity passing through gate up to 20% and the cell Peclet number less than 2.0 ensured no numerical oscillations.

Fabrication of silicon field emitter array using chemical-mechanical-polishing process (기계-화학적 연마 공정을 이용한 실리콘 전계방출 어레이의 제작)

  • 이진호;송윤호;강승열;이상윤;조경의
    • Journal of the Korean Vacuum Society
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    • v.7 no.2
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    • pp.88-93
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    • 1998
  • The fabrication process and emission characteristics of gated silicon field emitter arrays(FEAs) using chemical-mechanical-polishing (CMP) method are described. Novel fabrication techniques consisting of two-step dry etching with oxidation of silicon and CMP processes were developed for the formation of sharp tips and clear-cut edged gate electrodes, respectively. The gate height and aperture could be easily controlled by varying the polishing time and pressure in the CMP process. We obtained silicon FEAs having self-aligned and clear-cut edged gate electrode opening by eliminating the dishing problem during the CMP process with an oxide mask layer. The tip height of the finally fabricated FEAs was about 1.1 $\mu$m and the end radius of the tips was smaller than 100 $\AA$. The emission current meaured from the fabricated 2809 tips array was about 31 $\mu$A at a gate voltage of 80 V.

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