• Journal of Power Electronics
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• 제18권2호
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• pp.522-532
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• 2018

The cascaded H Bridge (CHB) multilevel inverter (MLI) is popular among the classical MLI topologies due to its modularity and reliability. Although space vector modulation (SVM) is the most suitable modulation scheme for MLIs, it has not been used widely in industry due to the higher complexity involved in its implementation. In this paper, a simple and novel generalized SVM algorithm is proposed, which has both reduced time and space complexity. The proposed SVM involves the generalization of both the duty cycle calculation and switching sequence generation for any n-level inverter. In order to generate the gate pulses for an inverter, a generalized switch matrix (SM) for the CHB inverter is also introduced, which further simplifies the algorithm. The algorithm is tested and verified for three-phase, three-level and five-level CHB inverters in simulations and hardware implementation. A comparison of the proposed method with existing SVM schemes shows the superiority of the proposed scheme.

• Journal of Power Electronics
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• 제16권2호
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• pp.498-511
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• 2016

This paper presents a single-phase five-level inverter controlled by two novel pulse width modulation (PWM) switching techniques. The proposed PWM techniques are designed based on minimum switching power loss and minimum total harmonic distortion (THD). In a single-phase five-level inverter employing six switches, the first proposed PWM technique requires four switches to operate at switching frequency and two other switches to operate at line frequency. The second proposed PWM technique requires only two switches to operate at switching frequency and the rest of the switches to operate at line frequency. Compared with conventional PWM techniques for single-phase five-level inverters, the proposed PWM techniques offer high efficiency and low harmonic components in the output voltage. The validity of the proposed PWM switching techniques in controlling single-phase five-level inverters to regulate load voltage is verified experimentally using a 100 V, 500 W laboratory prototype controlled by dspace 1103.

• 전력전자학회논문지
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• 제12권2호
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• pp.149-156
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• 2007

3상 변압기를 이용한 멀티레벨 인버터는 단상 변압기를 이용한 경우에 비해 변압기 수를 줄일 수 있으며, 변압기 이용률을 증대시켜 변압기 크기를 줄일 수 있다는 장점이 있으나 많은 수의 스위치 소자가 필요하다는 단점이 있다. 이에 본 논문에서는 공통암을 이용하여 스위치 수를 줄인 3상 변압기 절연 멀티레벨 인버터를 제안한다. 제안한 인버터는 스위칭 주파수를 기본주파수와 동일하게 제어하면서 등면적 법에 의해 도통각을 제어 하여 출력전압의 THD 감소 및 스위치 손실을 줄였다. 또한 Matlab을 이용한 시뮬레이션 및 실험을 통하여 제안된 방식의 타당성을 검증 하였다.

• 한국정보통신학회논문지
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• 제5권4호
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• pp.746-755
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• 2001

본 논문은 플라잉 커패시터 3-레벨 인버터 및 컨버터를 위한 스너버 회로를 제안하였다. 제안한 스너버회로는 Undeland 스너버를 기본 스너버로 사용하여 구성한 것으로서, 2-레벨 인버터에서 사용되어온 Undeland 스너버의 장점을 그대로 지니고 있다. 3-레벨 인버터 및 컨버터를 위해 제안한 스너버 회로와 기존의 RCD/RLD 스너버를 비교하면 1)사용소자의 수가 감소하며, 2) 낮은 과전압에 의한 스위칭 소자의 전압 스트레스가 감소하며, 3) 스너버 회로에서의 전력손실이 감소하여 전체 시스템에서의 효율이 개선된다. 본 논문에서는 제안한 스너버를 3-레벨 플라잉 커패시터 인버터에 적용하여 스너버 특성을 컴퓨터 시뮬레이션으로 분석하였으며 실험을 통해 제안한 스너버의 효용성을 입증하였다. 제안한 플라잉 커패시터 3-레벨 인버터 및 컨버터를 위한 스너버 회로를 구성하는 방법은 멀티레벨 인버터 및 컨버터에도 그대로 적용 할 수 있다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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• pp.23-26
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• 2003

This paper presents a novel hybrid type multilevel inverter in order to improve the waveshape of output voltage. The proposed multilevel inverter is consist of two full-bridge modules for level creation and one full-bridge module for PWM operation. The generated levels are total 11-level: 9-level by the level inverter and 2-level by the PWM inverter. The operational principles and analysis are explained and validity of the proposed system is verified through the experimental results using a prototype.

• Journal of Power Electronics
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• 제10권2호
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• pp.155-164
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• 2010

This paper presents a voltage control algorithm for a hybrid multilevel inverter based on a staged-perception of the inverter voltage vector diagram. The algorithm is applied to control a three-stage eighteen-level hybrid inverter, which has been designed with a maximum number of symmetrical levels. The inverter has a two-level main stage built using a conventional six-switch inverter and medium- and low- voltage three-level stages constructed using cascaded H-bridge cells. The distinctive feature of the proposed algorithm is its ability to avoid the undesirable high switching frequency for high- and medium- voltage stages despite the fact that the inverter's dc sources voltages are selected to maximize the number of levels by state redundancy elimination. The high- and medium- voltage stages switching algorithms have been developed to assure fundamental switching frequency operation of the high voltage stage and not more than few times this frequency for the medium voltage stage. The low voltage stage is controlled using a SVPWM to achieve the reference voltage vector exactly and to set the order of the dominant harmonics. The inverter has been constructed and the control algorithm has been implemented. Test results show that the proposed algorithm achieves the desired features and all of the major hypotheses have been verified.

• 전기학회논문지
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• 제67권2호
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• pp.209-215
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• 2018

This paper present a 7-level PWM inverter adopting voltage balancing control to series-connected input capacitors. The prior proposed 7-level PWM inverter consists of dc input source, three series-connected capacitors, two bidirectional switch modules, and an H-bridge. This circuit topology is useful to increase the number of output voltage levels, however it fails to generate 7-level in output voltage without consideration for voltage balancing among series-connected capacitors. Capacitor voltage imbalance is caused on the different period between charging and discharging of capacitor. To solve this problem, we uses the amplitude modulation of carrier wave, which is used to produce the center output voltage level. To verify the validity of the proposed control method, we carried out computer-aided simulation and experiments using a prototype.

• 전기학회논문지
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• 제64권2호
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• pp.268-275
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• 2015

This paper proposes a method of switching to improve power loss for the single-phase three-level NPC inverter. The conventional switching methods, which are called as the bipolar and unipolar switching methods, are used for single phase inverters using three-level topology. However, these switching method have disadvantage in the power loss. Because all of the switch are operated. To reduce the power loss of the three-level NPC inverter, clamp switching method is introduced in this paper. This way, one of the lag is fixed that switching loss is reduced. This paper analyzes and compares power losses of unipolar method and clamp method. The validity of the power loss analysis is verified through the simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• 제2권3호
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• pp.373-378
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• 2007

Soft switching was applied to the multi-level inverter to enhance the performance of the high-intensity discharge (HID) ballast used in vehicle headlights. The electrical properties were investigated and the available modeling of ballast in steady state was calculated using mathematical methods. The result was used in analyzing the power characteristics. The modeling was confirmed by the experiment.

• Journal of Electrical Engineering and Technology
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• 제12권2호
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• pp.701-710
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• 2017

This paper presents a five-level PWM inverter using series and parallel connection of voltage sources. The alternative connection is done by an auxiliary circuit consisted of a switch, three diodes, and two batteries. The auxiliary circuit is located between input dc voltage source and H-bridge cell. Thanks to the auxiliary circuit, the proposed inverter synthesizes five-level output voltage in an effective way. Topologically both batteries are charged and discharged in the same rate, so it does not need to apply battery voltage balancing control method. Theoretical analysis of the proposed inverter is verified by computer-aided simulation and experiment based on a prototype of 1kW.