• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.1
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• pp.54-68
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• 2001

This paper proposes a new algorithm that detects and separates the occluding and occluded objects in a 2D image. An input image is represented by the attributed graph where a node corresponds to a surface and an arc connecting two nodes describes the adjacency of the nodes in the image. Each end of arc is weighted by relation value which tells the number of edges connected to the surface represented by the node in the opposite side of the arc. In attributed graph, homogeneous nodes pertained to a same object always construct one of three special patterns which can be simply classified by comparison of relation values of the arcs. The experimental results have shown that the proposed algorithm efficiently separates the objects overlapped arbitrarily, and that this approach of separating objects before matching operation reduces the matching time significantly by simplifying the matching problem of overlapped objects as the one of individual single object.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.3
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• pp.493-501
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• 2020

For the obfuscation of Flow Analysis on the Android operating system, the size of the Flow Graph can be large enough to make analysis difficult. To this end, a library in the form of aar was implemented so that it could be inserted into the application in the form of an external library. The library is designed to have up to five child nodes from the entry point in the dummy code, and for each depth has 2n+1 numbers of methods from 100 to 900 for each node, so it consists of a total of 2,500 entry points. In addition, entry points consist of a total of 150 views in XML, each of which is connected via asynchronous interface. Thus, the process of creating a Inter-procedural Control Flow Graph has a maximum of 14,175E+11 additional cases. As a result of applying this to application, the Inter Procedure Control Flow Analysis too generates an average of 10,931 edges and 3,015 nodes with an average graph size increase of 36.64%. In addition, in the APK analyzing process showed that up to average 76.33MB of overhead, but only 0.88MB of execution overhead in the user's ART environment.

• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.179-186
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• 2011

This paper suggests the minimum number of vertex guards algorithm. Given n rooms, the exact number of minimum vertex guards is proposed. However, only approximation algorithms are presented about the maximum number of vertex guards for polygon and orthogonal polygon without or with holes. Fisk suggests the maximum number of vertex guards for polygon with n vertices as follows. Firstly, you can triangulate with n-2 triangles. Secondly, 3-chromatic vertex coloring of every triangulation of a polygon. Thirdly, place guards at the vertices which have the minority color. This paper presents the minimum number of vertex guards using dominating set. Firstly, you can obtain the visibility graph which is connected all edges if two vertices can be visible each other. Secondly, you can obtain dominating set from visibility graph or visibility matrix. This algorithm applies various art galley problems. As a results, the proposed algorithm is simple and can be obtain the minimum number of vertex guards.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.6
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• pp.165-173
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• 2012

Given a connected, weighted, and undirected graph, the Minimum Spanning Tree (MST) should have minimum sum of weights, connected all vertices, and without any cycle taking place. Borůvka Algorithm is firstly suggested as an algorithm to evaluate the MST, but it is not widely used rather than Prim and Kruskal algorithms. Borůvka algorithm selects the Minimum Weight Edge (MWE) from each vertex with distinct weights in $1^{st}$ stage, and selects the MWE from each MSF (Minimum Spanning Forest) in $2^{nd}$ stage. But the cycle check and the number of MSF in $1^{st}$ stage and $2^{nd}$ stage are difficult to implication by computer program even if it is easy to verify visually. This paper suggests the generalized Borůvka Algorithm, This algorithm selects all of the same MWEs for each vertex, then checks the cycle and constructs MSF for ascending sorted MWEs. Kruskal method bring into this process. if the number of MSF greats then 1, this algorithm selects MWE from ascending sorted inter-MSF edges. The generalized Borůvka algorithm is verified its application by being applied to the 7 graphs with the many minimum weights or distinct weight edges for any vertex. As a result, the generalized Borůvka algorithm is less required for cycle verification then the Kruskal algorithm. Therefore, the generalized Borůvka algorithm is more fast to obtain MST then Kruskal algorithm.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.209-218
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• 2012

Recently, the Field Programmable Stateful Logic Array (FPSLA) was proposed as one of the most promising system integration technologies which will extend the life of the Moore's law. This work is the first proposal of the FPSLA design automation flow, and the approaches to logic synthesis, synchronization, physical mapping, and automatic placement of the FPSLA designs. The synchronization at each gate for pipelining determines the x-coordinates of cells, and reduces the placement to 1-dimensional problems. The objective function and its gradients for the non-linear optimization of the net length and placement density have been remodeled for the reduced global placement problem. Also, a recursive algorithm has been proposed to legalize the placement by relaxing the density overflow of bipartite bin groups in a top-down hierarchical fashion. The proposed model and algorithm are implemented, and validated by applying them to the ACM/SIGDA benchmark designs. The output state of a gate in an FPSLA needs to be duplicated so that each fanout gate can be connected to a dedicated copy. This property has been taken into account by merging the duplicated nets into a hyperedge, and then, splitting the hyperedge into edges as the optimization progresses. This yields additional 18.4% of the cell count reduction in the most dense logic stage. The practicality of the FPSLA can be further enhanced primarily by incorporating into the logic synthesis the constraint to avoid the concentrated fains of gates on some logic stages. In addition, an efficient algorithm needs to be devised for the routing problem which is based on a complicated graph. The graph models the nanowire crossbar which is trimmed to be embedded into the FPSLA fabric, and therefore, asymmetric. These CAD tools can be used to evaluate the fabric efficiency during the architecture enhancement as well as automate the design.