• Journal of Power Electronics
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• 제18권1호
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• pp.212-224
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• 2018

For maintaining a reliable and secure power system, this paper describes the design and implement of a single-phase grid-connected inverter with an enhanced phase-locked loop (PLL) and excellent power control performance. For designing the enhanced PLL and power regulator, a full-bridge voltage-controlled inverter (VCI) is investigated. When the grid frequency deviates from its reference values, the output frequency of the VCI is unstable with an oscillation of 2 doubling harmonics. The reason for this oscillation is analyzed mathematically. This oscillation leads to an injection of harmonics into the grid and even causes an output active power oscillation of the VCI. For eliminating the oscillation caused by a PLL, an oscillation compensation method is proposed. With the proposed method, the VCI maintains the original PLL control characteristics and improves the PLL robustness under grid frequency deviations. On the basis of the above analysis, a power regulator with the primary frequency and voltage modulation characteristics is analyzed and designed. Meanwhile, a small-signal model of the power loops is established to determine the control parameters. The VCI can accurately output target power and has primary frequency and voltage modulation characteristics that can provide active and reactive power compensation to the grid. Finally, simulation and experimental results are given to verify the idea.

• 한국통신학회논문지
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• 제30권2A호
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• pp.122-128
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• 2005

본 논문에서는 고조파 억압 특성 개선을 위한 저잡음 병렬 궤환형 발진기 (Parallel feedback oscillator)와 주파수 체배기 (frequency doubler)를 설계 및 제작하였다. 주파수 체배를 위한 발진기의 기본 주파수를 유전체 공진기 (DR: Dielectric Resonator) 여파기와 능동소자 사이에서 얻음으로써 불요 고조파를 현저히 억압하였다. 발진기의 기본 주파수 신호는 고조파 신호를 억압하기 위한 부가적인 대역 통과 여파기가 필요치 않으며 곧바로 주파수 체배기의 입력단으로 인가되어 주파수 체배기의 입력 정합 회로가 간단하다. 측정된 발진기의 고조파 억압 특성은 -47.7 dBc이고 주파수 체배기를 이용하였을 때 24.0 GHz 에서의 기본 주파수 억압 특성은 -37.5 dBc이다. 위상 잡음 특성은 중심 주파수에서 10 KHz와 100 KHz 떨어진 곳에서 각각 -80.3 dBc/Hz와 -93.5 dBc/Hz이다.