• Title/Summary/Keyword: 2 doubling harmonics

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Power Control Strategies for Single-Phase Voltage-Controlled Inverters with an Enhanced PLL

  • Gao, Jiayuan;Zhao, Jinbin;He, Chaojie;Zhang, Shuaitao;Li, Fen
    • Journal of Power Electronics
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    • v.18 no.1
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    • pp.212-224
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    • 2018
  • For maintaining a reliable and secure power system, this paper describes the design and implement of a single-phase grid-connected inverter with an enhanced phase-locked loop (PLL) and excellent power control performance. For designing the enhanced PLL and power regulator, a full-bridge voltage-controlled inverter (VCI) is investigated. When the grid frequency deviates from its reference values, the output frequency of the VCI is unstable with an oscillation of 2 doubling harmonics. The reason for this oscillation is analyzed mathematically. This oscillation leads to an injection of harmonics into the grid and even causes an output active power oscillation of the VCI. For eliminating the oscillation caused by a PLL, an oscillation compensation method is proposed. With the proposed method, the VCI maintains the original PLL control characteristics and improves the PLL robustness under grid frequency deviations. On the basis of the above analysis, a power regulator with the primary frequency and voltage modulation characteristics is analyzed and designed. Meanwhile, a small-signal model of the power loops is established to determine the control parameters. The VCI can accurately output target power and has primary frequency and voltage modulation characteristics that can provide active and reactive power compensation to the grid. Finally, simulation and experimental results are given to verify the idea.

Parallel Feedback Oscillator for Strong Harmonics Suppression and Frequency Doubler (고조파 억압을 위한 병렬 궤환형 발진기와 주파수 체배기)

  • Lee, Kun-Joon;Ko, Jung-Pil;Kim, Young-Sik
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.2A
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    • pp.122-128
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    • 2005
  • In this paper, a low noise parallel feedback oscillator for harmonic suppression and a frequency doubler are designed and implemented. As the fundamental signal of the oscillator for frequency doubling is extracted between the dielectric resonator (DR) filter and the gate device of the active device, the undesired harmonics at the output of the oscillator is remarkably suppressed. The fundamental signal of the oscillator for frequency doubling directly feeds to the frequency doubler without an additional band pass filter for harmonic suppression. The second harmonic suppression of -47.7 dBc at the oscillator output is achieved, while the fundamental suppression of -37.5 dBc at the doubler output is obtained. The phase noise characteristics are -80.3 dBc/Hz and -93.5 dBc/Hz at the offset frequency of 10 KHz and 100 KHz from the carrier, respectively.