• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.211-214
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• 2000

In this paper, a discrete-time S-dimensional chaos circuit (S = 1,2,3,4,...) with array structure is proposed. By employing array structure which consists of 1-dimensional chaos circuits, the proposed circuit can achieve long working-life. This feature is favorable to exploit as a building block of chaos application systems to get into home electric appliances. Further more, the proposed circuit synthesized using switched-current (SI) techniques is suitable for integration. Concerning the proposed circuit, SPICE simulations are performed. SPICE simulations showed that the proposed circuit can generate the chaotic signals in spite of the fault of the building blocks of the proposed circuit. The proposed circuit is integrable by a standard BiCMOS technology.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• Journal of the Korean Society of Hazard Mitigation
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• v.5 no.2 s.17
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• pp.1-8
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• 2005

Microwave tomographic imaging technology using a bi-focusing operator has been developed in order to detect the internal voids/objects inside concrete structures. The imaging system consists of several cylindrical or planar array antennas for transmitting and receiving signals, and a numerical focusing operator is applied to the external signals both in transmitting and in receiving fields. In this study, the authors developed 3-dimensional (3D) electromagnetic (EM) imaging technology to detect such damage and to identify exact location of steel rebars or dowel. The authors have developed sub-surface two-dimensional (2D) imaging technique using tomographic antenna array in previous works. In this study, extending the earlier analytical and experimental works on 2D image reconstruction, a 3D microwave imaging system using tomographic antenna way was developed, and multi-frequency technique was applied to improve quality of the reconstructed image and to reduce background noises. Numerical simulation demonstrated that a sub-surface image can be successfully reconstructed by using the proposed tomographic imaging technology. For the experimental verification, a prototype antenna array was fabricated and tested on a concrete specimen.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.2
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• pp.411-418
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• 2018

This paper presents a novel three-dimensional (3D) object encryption scheme by combining the use of the virtual optics and the chaotic sequence. A virtual 3D object is digitally produced using a two-dimensional (2D) elemental image array (EIA) created with a virtual pinhole array. Then, through a logistic mapping of chaotic sequence, a final encrypted video can be produced. Such method converts the value of a pixel which is the basic information of an image. Therefore, it gives an improved encryption result compared to other existing methods. Through computational experiments, we were able to verify our method's feasibility and effectiveness.

• Food Science and Biotechnology
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• v.14 no.4
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• pp.554-557
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• 2005

As a device for taste sensation, an 8-channel taste evaluation system was prepared and applied for discriminant analysis of marketed liquor. The biomimetic polymer membranes for the system were prepared through a casting procedure by employing polyvinyl chloride, bis (2-ethylhexyl)sebacate as plasticizer and electroactive materials such as valinomycin in the ratio of 33:66:1, and were separately attached over the sensitive area of ion-selective electrodes to construct the corresponding taste sensor array. The sensor array in conjunction with a double junction reference electrode was connected to a high-input impedance amplifier and the amplified sensor signals were interfaced to a personal computer via an A/D converter. When the signal data from the sensor array for 3 groups of marketed liquor like Maesilju, Soju and beer were analyzed by principal component analysis after normalization, it was observed that the 1st, 2nd and 3rd principal component were responsible for most of the total data variance, and the analyzed liquor samples were discriminated well in 2 dimensional principal component planes composed of the 1st-2nd and the 1st-3rd principal component.

• The Journal of the Acoustical Society of Korea
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• v.20 no.2
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• pp.86-92
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• 2001

Various array processing techniques to identify the noise source position or bearing have been developed. Typical array processing techniques which are based on time delay between received signals at two sensors, are classified as conventional beamforming, correlation function and NAH (Near-Field Acoustic Holography) techniques which have their own characteristics with respect to application field and signal processing method. In this study, correlation function technique which could be applied for broadband noise source detection, is adopted and the effective detection technique is proposed considering the effects of source bandwidth and measurement noise correlation of noise sources. The validity of the Proposed technique is evaluated using the 3-dimensional nonlinear any which does not give 3-dimensional Position or bearing ambiguity

• Journal of the Korean Ceramic Society
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• v.55 no.2
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• pp.108-115
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• 2018

The increasing demands for three-dimensional (3D) electronic and optoelectronic devices have triggered interest in epitaxial growth of 3D semiconductor materials. However, most of the epitaxially-grown nano- and micro-structures available so far are limited to certain forms of crystal arrays, and the level of control is still very low. In this review, we describe our latest progress in 3D epitaxy of oxide and nitride semiconductor crystals. This paper covers issues ranging from (i) low-temperature solution-phase synthesis of a well-regulated array of ZnO single crystals to (ii) systematic control of the axial and lateral growth rate correlated to the diameter and interspacing of nanocrystals, as well as the concentration of additional ion additives. In addition, the critical aspects in the heteroepitaxial growth of GaN and InGaN multilayers on these ZnO nanocrystal templates are discussed to address its application to a 3D light emitting diode array.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.8
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• pp.758-764
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• 2015

This paper describes the pattern synthesis of array antenna which conforms to a metallic curved surface formed by the rotation of a quadratic function by using EAGA(Enhanced Adaptive Genetic Algorithm). Three rotated-type conformal surfaces are realized by changing the coefficient of the quadratic function and the pattern of each conformal array antenna is synthesized. In order to reduce the overall time of pattern synthesis, the transformed active element pattern obtained by the active element pattern of the 2-dimensional planar array using Euler angles rotation is utilized instead of the active element pattern of the 3-dimensional conformal array antenna itself. To verify validity of the proposed synthesis procedure, the synthesized patterns using EAGA are compared with those obtained by MWS.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.12
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• pp.1730-1736
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• 2015

This paper presents a 16-channel transimpedance amplifier (TIA) array implemented in a standard $0.18-{\mu}m$ CMOS technology for the applications of panoramic scan LADAR (PSL) systems. Since this array is the front-end circuits of the PSL systems to recover three dimensional image for unmanned vehicles, low-noise and high-gain characteristics are necessary. Thus, we propose a voltage-mode inverter TIA (I-TIA) array in this paper, of which measured results demonstrate that each channel of the array achieves $82-dB{\Omega}$ transimpedance gain, 565-MHz bandwidth for 0.5-pF photodiode capacitance, 6.7-pA/sqrt(Hz) noise current spectral density, and 33.8-mW power dissipation from a single 1.8-V supply. The measured eye-diagrams of the array confirm wide and clear eye-openings up to 1.3-Gb/s operations. Also, the optical pulse measurements estimate that the proposed 16-channel TIA array chip can detect signals within 20 meters away from the laser source. The whole chip occupies the area of $5.0{\times}1.1mm^2$ including I/O pads. For comparison, a current-mode 16-channel TIA array is also realized in the same $0.18-{\mu}m$ CMOS technology, which exploits regulated-cascode (RGC) input configuration. Measurements reveal that the I-TIA array achieves superior performance in optical pulse measurements.

• Journal of Information Display
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• v.13 no.2
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• pp.55-59
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• 2012

In this paper, a concept of an integrated elastomer substrate for a three-dimensional (3D) liquid crystal display based on the integral-imaging method is presented. The elemental lens array and columnar spacers were integrated into one of the two substrates, an elastomer substrate, through an imprinting process. The integrated elastomer substrate was capable of maintaining the uniform liquid crystal (LC) cell gap and promoting homeotropic LC alignment without any surface treatment. The monolithic approach reported herein will provide a key component for 3D displays with enhanced portability through a more than 40% weight reduction compared with the conventional integral-imaging method.