• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.33-40
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• 1992

The design method of signal delay line system using indirect frequency synthesizer is presented. The variable signal delay line system with 2[nsec] step of delay time at center frequency 60[MHz], bandwidth 500[KHz] and range 5.24-5.81[x10S0-6Tsec] is designed and fabricated. The results were met with good characteristics to be variable delay time of average 2.01[nsec] per step.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.2
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• pp.324-328
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• 2012

A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.

• ETRI Journal
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• v.40 no.6
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• pp.693-698
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• 2018

This paper presents a true-time delay (TTD) using a commercial $0.13-{\mu}m$ CMOS process for wideband phased-array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers (WDGAs), a 7-bit TTD circuit, and a 6-bit digital step attenuator (DSA) circuit. The T-type attenuator with a low-pass filter and the WDGAs are implemented for a low insertion loss error between the reference and time-delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB, respectively, at 2 GHz-18 GHz. The maximum time delay of 198 ps with a 1.56-ps step and the maximum attenuation of 31.5 dB with a 0.5-dB step are achieved at 2 GHz-18 GHz. The RMS time-delay and amplitude errors are <3 ps and <1 dB, respectively, at 2 GHz-18 GHz. An output P1 dB of <-0.5 dBm is achieved at 2 GHz-18 GHz. The chip size is $3.3{\times}1.6mm^2$, including pads, and the DC power consumption is 370 mW for a 3.3-V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2C
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• pp.181-192
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• 2003

Blind equalization of communication channel is important because it does not need training signal, nor does it require a priori channel information. So, we can increase the bandwidth efficiency. The linear prediction error method is perhaps the most attractive in practice due to the insensitive to blind channel equalizer length mismatch as well as for its simple adaptive implementation. Unfortunately, the previous one-step prediction error method is known to be limited in arbitrary decision delay. In this paper, we propose method for fractionally spaced blind equalizer with arbitrary decision delay using one-step forward prediction error filter from second-order statistics of the received signals for SIMO channel. Our algorithm utilizes the forward prediction error as training signal and computes the best decision delay from all possible decision delay. Simulation results are presented to demonstrate the performance of our proposed algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.119-126
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• 2007

This paper presents an efficient heuristic algorithm to avoid crosstalk which effects to delay of CMOS digital circuit by downsizing and upsizing of Gate. The proposed algorithm divide into two step, step1 performs downsizing of gate, step2 performs upsizing, so that avoid adjacent aggressor to critical path in series. The proposed algorithm has been verified on LGSynth91 benchmark circuits and Experimental results show an average 8.64% Crosstalk Avoidance effect. This result proved new potential of proposed algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.87-93
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• 2010

This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.193-197
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• 2013

This paper presents a 5-bit true time delay circuit using a standard 0.18 ${\mu}m$ CMOS process for the broadband phased array antenna without the beam squint. The maximum time delay of ~106 ps with the delay step of ~3.3 ps is achieved at 5-20 GHz. The RMS group delay and amplitude errors are < 1 ps and <2 dB, respectively. The measured insertion loss is <27 dB and the input and output return losses are <12 dB at 5-15 GHz. The current consumption is nearly zero with 1.8 V supply. The chip size is $1.04{\times}0.85\;mm^2$ including pads.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.2
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• pp.166-173
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• 1999

Reference models are used in many control algorithms for improvement of transient response characteristics. They provide desired trajectories that the plant should follow Most control systems have bounded control inputs to avoid saturation of the plant. If we design the reference models that do not account for limits of the control inputs, control performance of the system may be deteriorated. In this paper a new approach of avoiding saturation by varying the reference model for TDC(time delay control) based systems subject to step changes in the reference input. In this scheme, the variable reference model is determined based on the information on control inputs and the size of the step changes in the reference inputs. This scheme was verified by application to the BLDC motor position control system in simulations and experiments. The responses of the TDC with the variable reference model showed better tracking performance than that with the fixed reference model.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2298-2303
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• 2003

In this paper, very simple methods based on the exponential analysis are presented by which transfer function models for processes can easily be obtained. These methods employ step responses or impulse responses of the processes. These can also give a more precise transfer function model compared to the well-known graphical methods. Transfer functions are determined based on Prony method, which is one of the oldest and the most representative methods in the exponential analysis. Here, the method is reformed and applied to obtain the so-called low-order transfer function with pure time delay from the data of the step response. The effectiveness of the proposed method is examined through several numerical examples and experiments of the 2-tank level control process.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.9
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• pp.3496-3514
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• 2015

One of the challenging tasks in Mobile Ad hoc Network is to discover precise optimal routing solution due to the infrastructure-less dynamic behavior of wireless mobile nodes. Ant Colony Optimization, a swarm Intelligence technique, inspired by the foraging behaviour of ants in colonies was used in the past research works to compute the optimal path. In this paper, we propose a Recurrent Ant Colony Optimization (RECACO) that executes the actual Ant Colony Optimization iteratively based on recurrent value in order to obtain an optimal path convergence. Each iteration involves three steps: Pheromone tracking, Pheromone renewal and Node selection based on the residual energy in the mobile nodes. The novelty of our approach is the inclusion of new pheromone updating strategy in both online step-by-step pheromone renewal mode and online delayed pheromone renewal mode with the use of newly proposed metric named ELD (Energy Load Delay) based on energy, Load balancing and end-to-end delay metrics to measure the performance. RECACO is implemented using network simulator NS2.34. The implementation results show that the proposed algorithm outperforms the existing algorithms like AODV, ACO, LBE-ARAMA in terms of Energy, Delay, Packet Delivery Ratio and Network life time.