• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.921-929
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• 2011

This paper describes an analysis of the decoding performance and decoding convergence speed of layered LDPC(low-density parity-check) decoder for mobile WiMAX system, and the optimal design conditions for hardware implementation are searched. A fixed-point model of LDPC decoder, which is based on the min-sum algorithm and layered decoding scheme, is implemented and simulated using Matlab model. Through fixed-point simulations for the block lengths of 576, 1440, 2304 bits and the code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 specified in the IEEE 802.16e standard, the effect of internal bit-width, block length and code rate on the decoding performance are analyzed. Simulation results show that fixed-point bit-width larger than 8 bits with integer part of 5 bits should be used for acceptable decoding performance.

• The Journal of the Acoustical Society of Korea
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• v.19 no.7
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• pp.42-47
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• 2000

This paper describes a real-time implementation of a GSM-EFR (Global System for Mobil communications Enhanced Full Rate) speech coder using OakDSP core; a 16bit fixed-point Digital Signal Processor (DSP) by DSP Group, Inc. The real-time implemented speech coder required about 24MIPS for computation and 7.06K words and 12.19K words for code and data memory, respectively. The implemented GSM-EFR speech coder passes all of test vectors provided by ETSI (European Telecommunication Standard Institute), and perceptual speech quality measurement using MNB algorithm shows that the quality of the GSM-EFR speech coder is similar to the one of 32kbps ADPCM. The real-time implemented GSM-EFR speech coder which is the highest bit-rate mode of the GSM-AMR speech coder will be used as the basic structure of the GSM-AMR speech coder which is embedded in MODEM ASIC of IMT2000 asynchronous mode mobile station.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.1-8
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• 2018

Recently, the convolutional neural network shows high performance in many computer vision tasks. However, convolutional neural networks require enormous amount of operation, so it is difficult to adopt them in the embedded environments. To solve this problem, many studies are performed on the ASIC or FPGA implementation, where an efficient representation method is required. The fixed-point representation is adequate for the ASIC or FPGA implementation but causes a performance degradation. This paper proposes a separate optimization of representations for the convolutional layers and the batch normalization layers. With the proposed method, the required bit width for the convolutional layers is reduced from 16 bits to 10 bits for the ResNet-50 neural network. Since the computation amount of the convolutional layers occupies the most of the entire computation, the bit width reduction in the convolutional layers enables the efficient implementation of the convolutional neural networks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.4
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• pp.309-324
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• 1987

In recent years has been an increasing interest with respect to using the discrete cosine transform(DCT) of which performance is found close to that of the Karhumen-Loeve transform, known to be optimal in the area of digital image processing for tha purpose of the image data compression. Among most of reported algorithms aimed at lowering the coputation complexity. Chen's algorithm is is found to be most popular, Recently, Lee proposed a now algorithm of which the computational complexity is lower than that of Chen's. but its performance is significantly degraded by FWL(Finite-Word-Lenght) effects as a result of employinga a fixed-poing arithmetic. In this paper performance evaluation of these two algorithms and error analysis of FWL effect are described. Also a scaling technique which we call Up & Down-scaling is proposed to allevaiate a performance degradation due to fixed-point arithmetic. When the 16x16point 2DCT is applied on image data and a 16-bit fixed-point arithmetic is employed, both the analysis and simulation show that is colse to that of Chen's.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.6
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• pp.109-116
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• 2005

Recently, images/videos have been preferred as the communication media because of their information-implication and easy recognizability. But the amount of their data is so large that it has been the major research area to compress their data. This paper is related to optimization in th image data format, which can make a great effect in performance of data compression and is based on the wavelet transform and JPEG2000. This paper established a criterion to decide the data format to be used in wavelet transform, which is on the bases of the data errors in frequency transform and quantization. This criterion has been used to extract the optimal data format experimentally. The result were(1, 9) of 10-bit fixed-point format for filter coefficients and (9, 7) of 16-bit fixed-point data dormat for wavelet coefficients and their optimality was confirmed.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.257-260
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• 1999

We have designed a 32-bit RISC microprocessor with 16/32-bit fixed-point DSP functionality. This processor, called YRD-5, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP and load/store instructions with one or more issue latency cycles. High performance was achieved with these parallel functional units while adopting a sophisticated 5-stage pipeline structure and an improved DSP unit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.335-341
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• 1998

In this paper, we present a real time implementation of CS-ACELP(Conjugate Structure Algebraic Code Excited Linear Prediction) speech coder. ITU-T has standardized the CS-ACELP algorithm as G.729. Areal-time implementation of CS-ACELP speech coder algorithm is achieved using 16 bit fixed-point DSP chip. To implement in fixed-point DSP Chip, integer simulation of CS-ACELP algorithm is used. Furthermore. input/output function and communication function included in CS-ACELP speech coder is described. We develope CS-ACELP speech coder in DSP evaluation board and evaluate in IMT-2000 Test-bed.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.42 no.4
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• pp.7-14
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• 2005

Recently, images/videos have been preferred as the communication media because of their information-implication and easy recognizability. But the amount of their data is so large that it has been the major research area to compress their data. This paper is related to optimization in the image data format which can make a great effect in performance of data compression and is based on the wavelet transform and JPEG2000. This paper established a criterion to decide the data format to he used in wavelet transform which is on the bases of the data errors in frequency transform and quantization. This criterion has been used to extract the optimal data format experimentally. The result were (1, 9) of 10-bit fixed-point format for filter coefficients and (9, 7) of 16-bit fixed-point data format for wavelet coefficients and their optimality was confirmed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.713-720
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• 2012

Recently, holography has received much attention as the next generation visual technology. Hologram is obtained by the optical capturing, but in recent years it is mainly produced by the method using computer. This method is named by computer generated hologram (CGH). Since CGH requires huge computational amount, if it is implemented by S/W it can't work in real time. Therefore it should use FPGA or GPU for real time operation. If it is implemented in the type of H/W, it can't obtain the same quality as S/W due to the bit limitation of the internal system. In this paper, we analyze the bit width for minimizing the degradation of the hologram and reducing more hardware resources and propose guidelines for H/W implementation of CGH. To do this, we performs fixed-points simulations according to main internal variables and arithmetics, analyze the numerical and visual results, and present the optimal bit width according to application fields.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.145-148
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• 2000

본 논문은 범용 16bit Fixed-point DSP를 이용한 새로운 미국 DoD 2.4kbps MELP(Mixed Excitation Linear Predictive)보코더의 실시간 구현에 관한 것이다. 구현된 MELP보코더는 ROM 32.6kword, RAM 12.2kword를 가지며 40MIPS DSP에서 약 29MIPS를 필요로 하였다. 출력된 파형은 C simulator 와 Bit Exact한 출력 결과를 보여주었다. 실시간 구현된 MELP를 동일전송율의 2.4kbps AMBE와 음질 비교한 결과 AME보다는 MOS 0.2 음질 이 떨어졌다