• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.11
• /
• pp.2465-2473
• /
• 2012

Recently, as one of low complexity video encoding methods, DVC (Distributed Video Coding) scheme has been actively studied. Most of DVC schemes exploit feedback channel to achieve better coding performances, however, this causes these schemes to have high decoding delay. In order to overcome these, this paper proposes a new fast DVC decoding method using parity-bit request model, which can be obtained by using bit-error rate, sent by encoder with motion vector, which is transmitted through feedback channel by decoder after generating side information. Through several simulations, it is shown that the proposed method improves greatly the decoding speed, compared to the conventional schemes.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.8 s.338
• /
• pp.11-16
• /
• 2005

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

• KIPS Transactions on Computer and Communication Systems
• /
• v.11 no.1
• /
• pp.35-42
• /
• 2022

Visible light communication (VLC) is a method of transmitting data through LED blinking and is vulnerable to eavesdropping because the illumination affects the wide range of area. IEEE standard 802.15.7 defines On-Off Keying (OOK), Variable Pulse Position Modulation (VPPM), and Color Shift Keying (CSK) as modulation. In this paper, we propose an encryption method in VPPM for secure communication. The VPPM uses an encoding method called 4B6B where 16 different outputs are represented with 6-bit. This paper extends the number of outputs to 20, to add complexity while not violating the 4B6B generation conditions. Then each entry in the extended 4B6B table is scrambled using vigenère cipher. The probability of decrypting each 6-bit data is $\frac{1}{20}$. Eavesdropper should perform $\sum\limits_{k=1}^{n}20^k$ number of different trials to decrypt the message if the number of keys is n. The proposed method can be applied to OOK of PHY II and CSK of PHY III. We further discuss the secure encoding that can be used in OOK and CSK without performance degradation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.6
• /
• pp.420-435
• /
• 2001

As multimedia technology has rapidly grown recently, many researches to process multimedia data efficiently using general-purpose processors have been studied. In this paper, we proposed multimedia instructions which can process multimedia data effectively, and suggested a processor architecture for those instructions. The processor was described with Verilog-HDL in the behavioral level and simulated with CADENCE$^{TM}$ tool. Proposed multimedia instructions are total 48 instructions which can be classified into 7 groups. Multimedia data have 64-bit format and are processed as parallel subwords of 8-bit 8 bytes, 16-bit 4 half words or 32-bit 2 words. Modeled processor is developed based on the Integer Unit of SPARC V.9. It has five-stage pipeline RISC architecture with Harvard principle.e.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.6
• /
• pp.760-770
• /
• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.05a
• /
• pp.437-440
• /
• 2009

We propose a fast stream cipher ASC16 for software implementation. ASC16 has a very simple structure with ASR(Arithmetic Shift Register), NLF(Non-Linear Filter), and NLB(Non-Linear Block), and is executed by a word. It is a stream cipher for wireless communication, which makes 32bit key streams using s-box with non-linear transformation. The processed result is almost same as SSC2, 32bit output stream cipher, developed by Zhang, Carroll, and Chan. The period is longer than SSC2, and it causes the difficulty of Correlation attack and raises security very much. The proposed ASC16 is efficiently used in the process of a fast cipher in the limited environment such as wireless communication.

• Journal of the Optical Society of Korea
• /
• v.16 no.3
• /
• pp.203-209
• /
• 2012

Visible light communications (VLC) use modern solid-state light-emitting diodes (LEDs) to broadcast information. Emerging white-light LEDs allow the combination of lighting and optical wireless communication in one optical source. In this paper, a new LED lighting design using one-chip-type white LEDs is proposed for efficient illumination and optical wireless communications under the existence of several obstacles. Lighting and communication performance are analyzed to show the effectiveness of the proposed LED lighting. Specifically, the signal-to-noise ratio considering intersymbol interference and the bit-error rate of variable pulse position modulation (VPPM) with dimming control are considered.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.7
• /
• pp.1332-1339
• /
• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of information and communication convergence engineering
• /
• v.15 no.3
• /
• pp.160-164
• /
• 2017

Public key cryptography (PKC) is the basic building block for the cryptography applications such as encryption, key distribution, and digital signature scheme. Among many PKC, elliptic curve cryptography (ECC) is the most widely used in IT systems. Recently, very efficient Montgomery-Twisted-Edward (MoTE)-ECC was suggested, which supports low complexity for the finite field arithmetic, group operation, and scalar multiplication. However, we cannot directly adopt the MoTE-ECC to new PKC systems since the cryptography is not fully evaluated in terms of performance on the Internet of Things (IoT) platforms, which only supports very limited computation power, energy, and storage. In this paper, we fully evaluate the MoTE-ECC implementations on the representative IoT devices (16-bit MSP processors). The implementation is highly optimized for the target platform and compared in three different factors (ROM, RAM, and execution time). The work provides good reference results for a gradual transition from legacy ECC to MoTE-ECC on emerging IoT platforms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.10a
• /
• pp.311-314
• /
• 2003

This paper describes a virtual instrument system with faulty sensor reconstruction mechanism based on personal computer. This system consists of sensor control board using 16bit RISC machine, error signal reconstruction algorithm based on principal component analysis and auto tunned GUI interface according to the attached sensors. USB module is used for fast communication between PC and sensor controller. To show the veridity of the proposed system, the proposed system was applied to the developed sun tracker with 8 solar sensors.