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A Dithering Algorithm for Full-Color (16,777,216-Color) Support in an LCD with 6-bit Driver ICs

  • Lee, Seung-Woo;Kim, Sang-Soo
    • 한국정보디스플레이학회:학술대회논문집
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    • 2004.08a
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    • pp.389-392
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    • 2004
  • A new dithering algorithm, "Hi-FRC", to enable full (16,777,216) color display on LCD panel with 6-bit source D-IC's is presented. The conventional FRC can display only 16,194,277 colors. In addition, The LCD panel with Hi-FRC can meet the color grayscale linearity of TCO '03 because it can improve the color shift problem.

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A 200MHz high speed 16M SDRAM with negative delay circuit (부지연 회로를 내장한 200MHz 고속 16M SDRAM)

  • 김창선;장성진;김태훈;이재구;박진석;정웅식;전영현
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.4
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    • pp.16-25
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    • 1997
  • This paper shows a SDRAM opeating in 200MHz clock cycle which it use data interleave and pipelining for high speed operation. We proposed NdC (Negative DEaly circuit) to improve clock to access time(tAC) characteristics, also we proposed low power WL(wordline)driver circit and high efficiency VPP charge-pump circit. Our all circuits has been fabricated using 0.4um CMOS process, and the measured maximum speed is 200Mbytes/s in LvTTL interface.

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Enhancing the Debugger Performance for CDSP16V2 Processor (CDSP16V2 프로세서용 디버거 성능 향상)

  • Nam, Pyung-Yul;Kim, Seon-Wook
    • Proceedings of the Korean Information Science Society Conference
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    • 2011.06b
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    • pp.325-327
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    • 2011
  • 온보드 대상의 디버깅은 타깃머신의 처리 속도 및 통신 속도의 제약으로 인해 발생하는 지연시간 때문에 개발 기간이 길어지게 된다. 이런 문제를 해결하고자 소프트웨어 에뮬레이터를 상위 성능의 머신에서 구동하고 온보드로는 인스트럭션과 그에 필요한 데이터의 전송만 진행하여 온보드로부터의 메모리 전송을 최소화함으로써 지연시간을 감소시키는 효과를 얻을 수 있다. 본 논문에서는 Zaram사(社)의 CDSP16V2 프로세서를 위한 디버거 성능 개선 방법 및 구현에 대하여 서술한다.

와이브로+IPv6 컨버전스 표준화

  • Park, Su-Hong
    • TTA Journal
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    • s.103
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    • pp.36-40
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    • 2006
  • 지난해 11월초 열린 제64차 IETF(Internet Engineering Task Force) 국제 표준화회의에서는 휴대인터넷(WiBro, 와이브로) 서비스에 필요한 IPv6 기술표준을 제정할 표준 실무그룹인 16NG(IPv6 ove IEEE 802.16(e)Networks) 회의가 한국의 주도하에 신설되었다. 2006년 상반기, 세계 최초의 상용 서비스를 목표로 하는 우리나라의 와이브로 서비스의 해외시장 확산에 기여하게 될 이번 쾌거에 따라 TTA저널 2006년 신년호 인터뷰는 한국주도의 최초 IETF 워킹그룹 탄생에 의미를 부여하며 16NG에서 다루게 될“와이브로+IPv6 컨버전스 표준화”에 대하여 본 워킹그룹의 의장으로 선임예정인 삼성전자의 박수홍 선임연구원으로부터 관련 기술의 과거, 현재, 미래에 대하여 들어본다.

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Traffic Model in IEEE 802.16 BWA Environments (IEEE 802.16 BWA 환경에서의 트래픽 모델)

  • Koo, Hye-Ryun;Lim, Seog-Ku
    • Proceedings of the Korea Contents Association Conference
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    • 2004.11a
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    • pp.363-368
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    • 2004
  • 인터넷의 급속한 보급과 대용량 멀티미디어 서비스에 대한 요구 증가로 댁내 또는 중소사업장에 대한 광대역 무선 액세스(Broadband Wireless Access) 수요가 증가하고 있다. 본 논문에서는 ADSL이나 케이블 등의 유선 광대역 기술을 대체할 수 있는 IEEE 802.16 BWA 환경에서 시뮬레이션을 수행할 수 있는 트래픽 모델에 대해 설명한다.

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Computational Complexity Comparison of Second-Order Volterrra Filtering Algorithms

  • Im, Sungin
    • The Journal of the Acoustical Society of Korea
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    • v.16 no.2E
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    • pp.38-46
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    • 1997
  • The objective of the paper is to compare the computational complexity of five algorithms for computing time-domain second-order Volterra filter outputs in terms of number of real multiplication and addition operations required for implementation. This study shows that if the filter memory length is greater that or equal to 16, the fast algorithm using the overlap-save method and the frequency-domain symmetry properties of the quadratic coefficients is the most efficient among the algorithms investigated in this paper, When the filter memory length is less than 16, the algorithm using the time-domain symmetry properties is better than any other algorithm.

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ON CURVATURE PINCHING FOR TOTALLY REAL SUBMANIFOLDS OF $H^n$(c)

  • Matsuyama, Yoshio
    • Journal of the Korean Mathematical Society
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    • v.34 no.2
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    • pp.321-336
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    • 1997
  • Let S be the Ricci curvature of an n-dimensional compact minimal totally real submanifold M of a quaternion projective space $HP^n (c)$ of quaternion sectional curvature c. We proved that if $S \leq \frac{16}{3(n -2)}c$, then either $S \equiv \frac{4}{n - 1}c$ (i.e. M is totally geodesic or $S \equiv \frac{16}{3(n - 2)}c$. All compact minimal totally real submanifolds of $HP^n (c)$ satisfy in $S \equiv \frac{16}{3(n - 2)}c$ are determined.

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Effects of Electroacupuncture at Some Acupoints on the Cardiovascular System in Dogs Anesthetized with Tiletamine/zolazepam (Tiletamine/zolazepam 마취견에서 전침자극이 순환기계에 미치는 영향)

  • 강한샘;장환수;이문학;엄기동;장광호
    • Journal of Veterinary Clinics
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    • v.20 no.2
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    • pp.224-228
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    • 2003
  • This study was performed to evaluate the effect of electroacupuncture at some acupoint combinations on the cardiovascular system, especially on blood pressure. Electroacupuncture at acupoint combinations of CV2O(+)/GV-16(-),4(+)/GV16(-), KI1(+)/GV20(-), and HT9(+)/GV16(-) did not changed heart rates and blood pressure, but stimulation of HT1(+)/HT7(-) Increased systolic, diastolic and mean arterial blood pressure significantly in dogs anesthetized with tiletamine/zolazepam.

Seamless Handover with Motion Prediction in 802.16e (휴대인터넷에서 움직임 예측을 이용한 seamless handover 방법)

  • Lee, Ho-Jeong;Yun, Chan-Young;Oh, Young-Hwan
    • Proceedings of the KIEE Conference
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    • 2005.10b
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    • pp.397-399
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    • 2005
  • Handover is one of the most important factors that may degrade the performance of TCP connections and real-time applications in wireless data networks. We proposed a seamless handover with Motion Prediction in IEEE 802.16e-based broadband wireless access networks. By intergrating MAC and network layer handovers efficiently, this scheme minimizes the handover delay and eliminates packet losses during handover Simulations show that this scheme achieves loss-free packet delivery without packet duplication and increases TCP throughput significantly.

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Design & Verification of 16 Bit RISC Processor (16 비트 RISC 프로세서 설계 및 검증)

  • Jung, Seung-Pyo;Song, Seung-Won;Lee, Dong-Hoon;Kim, Kang-Joo;Cho, Koon-Shik;Park, Ju-Sung
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.423-424
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    • 2008
  • The procedure of design and verification for a 16-bit RISC processor is introduced in this paper. The proposed processor has Harvard architecture and consists of 24-bit address, 5-stage pipeline instruction execution, and internal debug logic. ADPCM vocoder and SOLA algorithm are successfully carried out on the processor made with FPGA.

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